B2.4 AArch64 registers by functional group

This section identifies the AArch64 registers by their functional groups and applies to the registers in the core that are implementation defined or have micro-architectural bit fields. Reset values are provided for these registers.

Identification registers

Name Type Reset Description
AIDR_EL1 RO

0x00000000

B2.14 AIDR_EL1, Auxiliary ID Register, EL1

CCSIDR__EL1 RO

-

B2.23 CCSIDR_EL1, Cache Size ID Register, EL1

CLIDR_EL1 RO
  • 0xC3000123 if L3 cache present.
  • 0x82000023 if no L3 cache.

B2.24 CLIDR_EL1, Cache Level ID Register, EL1

CSSELR_EL1 RW

UNK

B2.38 CSSELR_EL1, Cache Size Selection Register, EL1

CTR_EL0 RO

0x8444C004

B2.39 CTR_EL0, Cache Type Register, EL0

DCZID_EL0 RO 0x00000004 B2.40 DCZID_EL0, Data Cache Zero ID Register, EL0
ERRIDR_EL1 RO 0x00000002 B2.42 ERRIDR_EL1, Error ID Register, EL1
ID_AA64AFR0_EL1 RO 0x00000000 B2.58 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0
ID_AA64AFR1_EL1 RO 0x00000000 B2.59 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1
ID_AA64DFR0_EL1 RO

0x0000000010305408

B2.60 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0, EL1

ID_AA64DFR1_EL1 RO 0x00000000 B2.61 ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1, EL1
ID_AA64ISAR0_EL1 RO
  • 0x0000100010211120 if the Cryptographic Extension is implemented.
  • 0x0000100010210000 if the Cryptographic Extension is not implemented.

B2.62 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1

ID_AA64ISAR1_EL1 RO

0x0000000000100001

B2.63 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1

ID_AA64MMFR0_EL1 RO

0x0000000000101122

B2.64 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1

ID_AA64MMFR1_EL1 RO

0x0000000010212122

B2.65 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1

ID_AA64MMFR2_EL1 RO

0x0000000000001011

B2.66 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1

ID_AA64PFR0_EL1 RO
  • 0x1100000010111112 if the GICv4 interface is disabled.
  • 0x1100000011111112 if the GICv4 interface is enabled.

B2.67 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1

ID_AA64PFR1_EL1 RO 0x0000000000000010 B2.68 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1
ID_AFR0_EL1 RO

0x00000000

B2.69 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0, EL1

ID_DFR0_EL1 RO

0x04010088

B2.70 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1

ID_ISAR0_EL1 RO

0x02101110

B2.71 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1

ID_ISAR1_EL1 RO

0x13112111

B2.72 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1

ID_ISAR2_EL1 RO

0x21232042

B2.73 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1

ID_ISAR3_EL1 RO

0x01112131

B2.74 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1

ID_ISAR4_EL1 RO

0x00010142

B2.75 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1

ID_ISAR5_EL1 RO

0x01011121

ID_ISAR5 has the value 0x01010001 if the Cryptographic Extension is not implemented and enabled.

B2.76 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1

ID_ISAR6_EL1 RO

0x00000010

B2.77 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1

ID_MMFR0_EL1 RO

0x10201105

B2.78 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1

ID_MMFR1_EL1 RO

0x40000000

B2.79 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1

ID_MMFR2_EL1 RO

0x01260000

B2.80 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1

ID_MMFR3_EL1 RO

0x02122211

B2.81 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1

ID_MMFR4_EL1 RO

0x00021110

B2.82 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1

ID_PFR0_EL1 RO

0x10010131

B2.83 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1

ID_PFR1_EL1 RO

0x10010000

Bits [31:28] are 0x1 if the GIC CPU interface is implemented and enabled, and 0x0 otherwise.

B2.84 ID_PFR1_EL1, AArch32 Processor Feature Register 1, EL1

ID_PFR2_EL1 RO

0x00000011

B2.85 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1

LORID_EL1 RO

0x0000000000040004

B2.87 LORID_EL1, LORegion ID Register, EL1

MIDR_EL1 RO

0x414FD0B0

B2.90 MIDR_EL1, Main ID Register, EL1

MPIDR_EL1 RO

The reset value depends on CLUSTERIDAFF2[7:0] and CLUSTERIDAFF3[7:0]. See register description for details.

B2.91 MPIDR_EL1, Multiprocessor Affinity Register, EL1

REVIDR_EL1 RO

0x00000000

B2.93 REVIDR_EL1, Revision ID Register, EL1

VMPIDR_EL2 RW

The reset value is the value of MPIDR_EL1.

Virtualization Multiprocessor ID Register EL2

VPIDR_EL2 RW

The reset value is the value of MIDR_EL1.

Virtualization Core ID Register EL2

Virtual Memory control registers

Name Type Description
AMAIR_EL1 RW

B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1

AMAIR_EL2 RW

B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2

AMAIR_EL3 RW

B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3

ATCR_EL1 RW

B2.18 ATCR_EL1, Auxiliary Translation Control Register, EL1

ATCR_EL2 RW

B2.19 ATCR_EL2, Auxiliary Translation Control Register, EL2

ATCR_EL12 RW

B2.20 ATCR_EL12 , Alias to Auxiliary Translation Control Register EL1

ATCR_EL3 RW

B2.21 ATCR_EL3, Auxiliary Translation Control Register, EL3

AVTCR_EL2 RW

B2.22 AVTCR_EL2, Auxiliary Virtualized Translation Control Register, EL2

LORC_EL1 RW

B2.86 LORC_EL1, LORegion Control Register, EL1

LOREA_EL1 RW

LORegion End Address Register EL1

LORID_EL1 RO

B2.87 LORID_EL1, LORegion ID Register, EL1

LORN_EL1 RW

B2.88 LORN_EL1, LORegion Number Register, EL1

LORSA_EL1 RW

LORegion Start Address Register EL1

TCR_EL1 RW

B2.99 TCR_EL1, Translation Control Register, EL1

TCR_EL2 RW

B2.100 TCR_EL2, Translation Control Register, EL2

TCR_EL3 RW

B2.101 TCR_EL3, Translation Control Register, EL3

TTBR0_EL1 RW

B2.102 TTBR0_EL1, Translation Table Base Register 0, EL1

TTBR0_EL2 RW

B2.103 TTBR0_EL2, Translation Table Base Register 0, EL2

TTBR0_EL3 RW

B2.104 TTBR0_EL3, Translation Table Base Register 0, EL3

TTBR1_EL1 RW

B2.105 TTBR1_EL1, Translation Table Base Register 1, EL1

TTBR1_EL2 RW

B2.106 TTBR1_EL2, Translation Table Base Register 1, EL2

VTTBR_EL2 RW

B2.110 VTTBR_EL2, Virtualization Translation Table Base Register, EL2

The following table shows the 32-bit wide implementation defined Cluster registers. Details of these registers can be found in Arm® DynamIQ™ Shared Unit Technical Reference Manual

Table B2-5 Cluster registers

Name Copro CRn Opc1 CRm Opc2 Width Description
CLUSTERCFR_EL1 3 c15 0 c3 0 32-bit Cluster configuration register.
CLUSTERIDR_EL1 3 c15 0 c3 1 32-bit Cluster main revision ID.
CLUSTEREVIDR_EL1 3 c15 0 c3 2 32-bit Cluster ECO ID.
CLUSTERACTLR_EL1 3 c15 0 c3 3 32-bit Cluster auxiliary control register.
CLUSTERECTLR_EL1 3 c15 0 c3 4 32-bit Cluster extended control register.
CLUSTERPWRCTLR_EL1 3 c15 0 c3 5 32-bit Cluster power control register.
CLUSTERPWRDN_EL1 3 c15 0 c3 6 32-bit Cluster power down register.
CLUSTERPWRSTAT_EL1 3 c15 0 c3 7 32-bit Cluster power status register.
CLUSTERTHREADSID_EL1 3 c15 0 c4 0 32-bit Cluster thread scheme ID register.
CLUSTERACPSID_EL1 3 c15 0 c4 1 32-bit Cluster ACP scheme ID register.
CLUSTERSTASHSID_EL1 3 c15 0 c4 2 32-bit Cluster stash scheme ID register.
CLUSTERPARTCR_EL1 3 c15 0 c4 3 32-bit Cluster partition control register.
CLUSTERBUSQOS_EL1 3 c15 0 c4 4 32-bit Cluster bus QoS control register.
CLUSTERL3HIT_EL1 3 c15 0 c4 5 32-bit Cluster L3 hit counter register.
CLUSTERL3MISS_EL1 3 c15 0 c4 6 32-bit Cluster L3 miss counter register.
CLUSTERTHREADSIDOVR_EL1 3 c15 0 c4 7 32-bit Cluster thread scheme ID override register
CLUSTERPMCR_EL1 3 c15 0 c5 0 32-bit Cluster Performance Monitors Control Register
CLUSTERPMCNTENSET_EL1 3 c15 0 c5 1 32-bit Cluster Count Enable Set Register
CLUSTERPMCNTENCLR_EL1 3 c15 0 c5 2 32-bit Cluster Count Enable Clear Register
CLUSTERPMOVSSET_EL1 3 c15 0 c5 3 32-bit Cluster Overflow Flag Status Set
CLUSTERPMOVSCLR_EL1 3 c15 0 c5 4 32-bit Cluster Overflow Flag Status Clear
CLUSTERPMSELR_EL1 3 c15 0 c5 5 32-bit Cluster Event Counter Selection Register
CLUSTERPMINTENSET_EL1 3 c15 0 c5 6 32-bit Cluster Interrupt Enable Set Register
CLUSTERPMINTENCLR_EL1 3 c15 0 c5 7 32-bit Cluster Interrupt Enable Clear Register
CLUSTERPMXEVTYPER_EL1 3 c15 0 c6 1 32-bit Cluster Selected Event Type and Filter Register
CLUSTERPMXEVCNTR_EL1 3 c15 0 c6 2 32-bit Cluster Selected Event Counter Register
Reserved/RAZ 3 c15 0 c6 3 32-bit Cluster Monitor Debug Configuration Register
CLUSTERPMCEID0_EL1 3 c15 0 c6 4 32-bit Cluster Common Event Identification ID0 Register
CLUSTERPMCEID1_EL1 3 c15 0 c6 5 32-bit Cluster Common Event Identification ID1 Register
CLUSTERPMCLAIMSET_EL1 3 c15 0 c6 6 32-bit Cluster Performance Monitor Claim Tag Set Register
CLUSTERPMCLAIMCLR_EL1 3 c15 0 c6 7 32-bit Cluster Performance Monitor Claim Tag Clear Register

Reset management registers

Address registers

Name Type Description
PAR_EL1 RW

B2.92 PAR_EL1, Physical Address Register, EL1

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