Part B Register descriptions

Table of Contents

B1 AArch32 system registers
B1.1 AArch32 architectural system register summary
B2 AArch64 system registers
B2.1 AArch64 registers
B2.2 AArch64 architectural system register summary
B2.3 AArch64 implementation defined register summary
B2.4 AArch64 registers by functional group
B2.5 ACTLR_EL1, Auxiliary Control Register, EL1
B2.6 ACTLR_EL2, Auxiliary Control Register, EL2
B2.7 ACTLR_EL3, Auxiliary Control Register, EL3
B2.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1
B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2
B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3
B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1
B2.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2
B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3
B2.14 AIDR_EL1, Auxiliary ID Register, EL1
B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1
B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2
B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3
B2.18 ATCR_EL1, Auxiliary Translation Control Register, EL1
B2.19 ATCR_EL2, Auxiliary Translation Control Register, EL2
B2.20 ATCR_EL12 , Alias to Auxiliary Translation Control Register EL1
B2.21 ATCR_EL3, Auxiliary Translation Control Register, EL3
B2.22 AVTCR_EL2, Auxiliary Virtualized Translation Control Register, EL2
B2.23 CCSIDR_EL1, Cache Size ID Register, EL1
B2.24 CLIDR_EL1, Cache Level ID Register, EL1
B2.25 CPACR_EL1, Architectural Feature Access Control Register, EL1
B2.26 CPTR_EL2, Architectural Feature Trap Register, EL2
B2.27 CPTR_EL3, Architectural Feature Trap Register, EL3
B2.28 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1
B2.29 CPUACTLR2_EL1, CPU Auxiliary Control Register 2, EL1
B2.30 CPUACTLR3_EL1, CPU Auxiliary Control Register 3, EL1
B2.31 CPUCFR_EL1, CPU Configuration Register, EL1
B2.32 CPUECTLR_EL1, CPU Extended Control Register, EL1
B2.33 CPUPCR_EL3, CPU Private Control Register, EL3
B2.34 CPUPMR_EL3, CPU Private Mask Register, EL3
B2.35 CPUPOR_EL3, CPU Private Operation Register, EL3
B2.36 CPUPSELR_EL3, CPU Private Selection Register, EL3
B2.37 CPUPWRCTLR_EL1, Power Control Register, EL1
B2.38 CSSELR_EL1, Cache Size Selection Register, EL1
B2.39 CTR_EL0, Cache Type Register, EL0
B2.40 DCZID_EL0, Data Cache Zero ID Register, EL0
B2.41 DISR_EL1, Deferred Interrupt Status Register, EL1
B2.42 ERRIDR_EL1, Error ID Register, EL1
B2.43 ERRSELR_EL1, Error Record Select Register, EL1
B2.44 ERXADDR_EL1, Selected Error Record Address Register, EL1
B2.45 ERXCTLR_EL1, Selected Error Record Control Register, EL1
B2.46 ERXFR_EL1, Selected Error Record Feature Register, EL1
B2.47 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1
B2.48 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1
B2.49 ERXPFGCDN_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1
B2.50 ERXPFGCTL_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
B2.51 ERXPFGF_EL1, Selected Pseudo Fault Generation Feature Register, EL1
B2.52 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1
B2.53 ESR_EL1, Exception Syndrome Register, EL1
B2.54 ESR_EL2, Exception Syndrome Register, EL2
B2.55 ESR_EL3, Exception Syndrome Register, EL3
B2.56 HACR_EL2, Hyp Auxiliary Configuration Register, EL2
B2.57 HCR_EL2, Hypervisor Configuration Register, EL2
B2.58 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0
B2.59 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1
B2.60 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0, EL1
B2.61 ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1, EL1
B2.62 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1
B2.63 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1
B2.64 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1
B2.65 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1
B2.66 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1
B2.67 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
B2.68 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1
B2.69 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0, EL1
B2.70 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1
B2.71 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1
B2.72 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1
B2.73 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1
B2.74 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1
B2.75 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1
B2.76 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1
B2.77 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1
B2.78 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1
B2.79 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1
B2.80 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1
B2.81 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1
B2.82 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1
B2.83 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1
B2.84 ID_PFR1_EL1, AArch32 Processor Feature Register 1, EL1
B2.85 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1
B2.86 LORC_EL1, LORegion Control Register, EL1
B2.87 LORID_EL1, LORegion ID Register, EL1
B2.88 LORN_EL1, LORegion Number Register, EL1
B2.89 MDCR_EL3, Monitor Debug Configuration Register, EL3
B2.90 MIDR_EL1, Main ID Register, EL1
B2.91 MPIDR_EL1, Multiprocessor Affinity Register, EL1
B2.92 PAR_EL1, Physical Address Register, EL1
B2.93 REVIDR_EL1, Revision ID Register, EL1
B2.94 RMR_EL3, Reset Management Register
B2.95 RVBAR_EL3, Reset Vector Base Address Register, EL3
B2.96 SCTLR_EL1, System Control Register, EL1
B2.97 SCTLR_EL2, System Control Register, EL2
B2.98 SCTLR_EL3, System Control Register, EL3
B2.99 TCR_EL1, Translation Control Register, EL1
B2.100 TCR_EL2, Translation Control Register, EL2
B2.101 TCR_EL3, Translation Control Register, EL3
B2.102 TTBR0_EL1, Translation Table Base Register 0, EL1
B2.103 TTBR0_EL2, Translation Table Base Register 0, EL2
B2.104 TTBR0_EL3, Translation Table Base Register 0, EL3
B2.105 TTBR1_EL1, Translation Table Base Register 1, EL1
B2.106 TTBR1_EL2, Translation Table Base Register 1, EL2
B2.107 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2
B2.107.1 VDISR_EL2 at EL1 using AArch64
B2.108 VSESR_EL2, Virtual SError Exception Syndrome Register
B2.109 VTCR_EL2, Virtualization Translation Control Register, EL2
B2.110 VTTBR_EL2, Virtualization Translation Table Base Register, EL2
B3 Error system registers
B3.1 Error system register summary
B3.2 ERR0ADDR, Error Record Address Register
B3.3 ERR0CTLR, Error Record Control Register
B3.4 ERR0FR, Error Record Feature Register
B3.5 ERR0MISC0, Error Record Miscellaneous Register 0
B3.6 ERR0MISC1, Error Record Miscellaneous Register 1
B3.7 ERR0PFGCDN, Error Pseudo Fault Generation Count Down Register
B3.8 ERR0PFGCTL, Error Pseudo Fault Generation Control Register
B3.9 ERR0PFGF, Error Pseudo Fault Generation Feature Register
B3.10 ERR0STATUS, Error Record Primary Status Register
B4 GIC registers
B4.1 CPU interface registers
B4.2 AArch64 physical GIC CPU interface system register summary
B4.3 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0 Register 0, EL1
B4.4 ICC_AP1R0_EL1, Interrupt Controller Active Priorities Group 1 Register 0 EL1
B4.5 ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0, EL1
B4.6 ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1, EL1
B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1
B4.8 ICC_CTLR_EL3, Interrupt Controller Control Register, EL3
B4.9 ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1
B4.10 ICC_SRE_EL2, Interrupt Controller System Register Enable register, EL2
B4.11 ICC_SRE_EL3, Interrupt Controller System Register Enable register, EL3
B4.12 AArch64 virtual GIC CPU interface register summary
B4.13 ICV_AP0R0_EL1, Interrupt Controller Virtual Active Priorities Group 0 Register 0, EL1
B4.14 ICV_AP1R0_EL1, Interrupt Controller Virtual Active Priorities Group 1 Register 0, EL1
B4.15 ICV_BPR0_EL1, Interrupt Controller Virtual Binary Point Register 0, EL1
B4.16 ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1, EL1
B4.17 ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1
B4.18 AArch64 virtual interface control system register summary
B4.19 ICH_AP0R0_EL2, Interrupt Controller Hyp Active Priorities Group 0 Register 0, EL2
B4.20 ICH_AP1R0_EL2, Interrupt Controller Hyp Active Priorities Group 1 Register 0, EL2
B4.21 ICH_HCR_EL2, Interrupt Controller Hyp Control Register, EL2
B4.22 ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register, EL2
B4.23 ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2
B5 Advanced SIMD and floating-point registers
B5.1 AArch64 register summary
B5.2 FPCR, Floating-point Control Register
B5.3 FPSR, Floating-point Status Register
B5.4 MVFR0_EL1, Media and VFP Feature Register 0, EL1
B5.5 MVFR1_EL1, Media and VFP Feature Register 1, EL1
B5.6 MVFR2_EL1, Media and VFP Feature Register 2, EL1
B5.7 AArch32 register summary
B5.8 FPSCR, Floating-Point Status and Control Register
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