Part D Debug registers

Table of Contents

D1 AArch32 debug registers
D1.1 AArch32 debug register summary
D2 AArch64 debug registers
D2.1 AArch64 debug register summary
D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
D2.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1
D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
D3 Memory-mapped debug registers
D3.1 Memory-mapped debug register summary
D3.2 EDCIDR0, External Debug Component Identification Register 0
D3.3 EDCIDR1, External Debug Component Identification Register 1
D3.4 EDCIDR2, External Debug Component Identification Register 2
D3.5 EDCIDR3, External Debug Component Identification Register 3
D3.6 EDDEVID, External Debug Device ID Register 0
D3.7 EDDEVID1, External Debug Device ID Register 1
D3.8 EDPIDR0, External Debug Peripheral Identification Register 0
D3.9 EDPIDR1, External Debug Peripheral Identification Register 1
D3.10 EDPIDR2, External Debug Peripheral Identification Register 2
D3.11 EDPIDR3, External Debug Peripheral Identification Register 3
D3.12 EDPIDR4, External Debug Peripheral Identification Register 4
D3.13 EDPIDRn, External Debug Peripheral Identification Registers 5-7
D3.14 EDRCR, External Debug Reserve Control Register
D4 AArch32 PMU registers
D4.1 AArch32 PMU register summary
D4.2 PMCEID0, Performance Monitors Common Event Identification Register 0
D4.3 PMCEID1, Performance Monitors Common Event Identification Register 1
D4.4 PMCR, Performance Monitors Control Register
D5 AArch64 PMU registers
D5.1 AArch64 PMU register summary
D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0
D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0
D5.4 PMCR_EL0, Performance Monitors Control Register, EL0
D6 Memory-mapped PMU registers
D6.1 Memory-mapped PMU register summary
D6.2 PMCFGR, Performance Monitors Configuration Register
D6.3 PMCIDR0, Performance Monitors Component Identification Register 0
D6.4 PMCIDR1, Performance Monitors Component Identification Register 1
D6.5 PMCIDR2, Performance Monitors Component Identification Register 2
D6.6 PMCIDR3, Performance Monitors Component Identification Register 3
D6.7 PMPIDR0, Performance Monitors Peripheral Identification Register 0
D6.8 PMPIDR1, Performance Monitors Peripheral Identification Register 1
D6.9 PMPIDR2, Performance Monitors Peripheral Identification Register 2
D6.10 PMPIDR3, Performance Monitors Peripheral Identification Register 3
D6.11 PMPIDR4, Performance Monitors Peripheral Identification Register 4
D6.12 PMPIDRn, Performance Monitors Peripheral Identification Register 5-7
D7 PMU snapshot registers
D7.1 PMU snapshot register summary
D7.2 PMPCSSR, Snapshot Program Counter Sample Register
D7.3 PMCIDSSR, Snapshot CONTEXTIDR_EL1 Sample Register
D7.4 PMCID2SSR, Snapshot CONTEXTIDR_EL2 Sample Register
D7.5 PMSSSR, PMU Snapshot Status Register
D7.6 PMOVSSR, PMU Overflow Status Snapshot Register
D7.7 PMCCNTSR, PMU Cycle Counter Snapshot Register
D7.8 PMEVCNTSRn, PMU Cycle Counter Snapshot Registers 0-5
D7.9 PMSSCR, PMU Snapshot Capture Register
D8 AArch64 AMU registers
D8.1 AArch64 AMU register summary
D8.2 AMCNTENCLR_EL0, Activity Monitors Count Enable Clear Register, EL0
D8.3 AMCNTENSET_EL0, Activity Monitors Count Enable Set Register, EL0
D8.4 AMCFGR_EL0, Activity Monitors Configuration Register, EL0
D8.5 AMUSERENR_EL0, Activity Monitor EL0 Enable access, EL0
D8.6 AMEVCNTRn_EL0, Activity Monitor Event Counter Register, EL0
D8.7 AMEVTYPERn_EL0, Activity Monitor Event Type Register, EL0
D9 Memory-mapped AMU registers
D9.1 Memory-mapped AMU register summary
D10 ETM registers
D10.1 ETM register summary
D10.2 TRCACATRn, Address Comparator Access Type Registers 0-7
D10.3 TRCACVRn, Address Comparator Value Registers 0-7
D10.4 TRCAUTHSTATUS, Authentication Status Register
D10.5 TRCAUXCTLR, Auxiliary Control Register
D10.6 TRCBBCTLR, Branch Broadcast Control Register
D10.7 TRCCCCTLR, Cycle Count Control Register
D10.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0
D10.9 TRCCIDCVR0, Context ID Comparator Value Register 0
D10.10 TRCCIDR0, ETM Component Identification Register 0
D10.11 TRCCIDR1, ETM Component Identification Register 1
D10.12 TRCCIDR2, ETM Component Identification Register 2
D10.13 TRCCIDR3, ETM Component Identification Register 3
D10.14 TRCCLAIMCLR, Claim Tag Clear Register
D10.15 TRCCLAIMSET, Claim Tag Set Register
D10.16 TRCCNTCTLR0, Counter Control Register 0
D10.17 TRCCNTCTLR1, Counter Control Register 1
D10.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1
D10.19 TRCCNTVRn, Counter Value Registers 0-1
D10.20 TRCCONFIGR, Trace Configuration Register
D10.21 TRCDEVAFF0, Device Affinity Register 0
D10.22 TRCDEVAFF1, Device Affinity Register 1
D10.23 TRCDEVARCH, Device Architecture Register
D10.24 TRCDEVID, Device ID Register
D10.25 TRCDEVTYPE, Device Type Register
D10.26 TRCEVENTCTL0R, Event Control 0 Register
D10.27 TRCEVENTCTL1R, Event Control 1 Register
D10.28 TRCEXTINSELR, External Input Select Register
D10.29 TRCIDR0, ID Register 0
D10.30 TRCIDR1, ID Register 1
D10.31 TRCIDR2, ID Register 2
D10.32 TRCIDR3, ID Register 3
D10.33 TRCIDR4, ID Register 4
D10.34 TRCIDR5, ID Register 5
D10.35 TRCIDR8, ID Register 8
D10.36 TRCIDR9, ID Register 9
D10.37 TRCIDR10, ID Register 10
D10.38 TRCIDR11, ID Register 11
D10.39 TRCIDR12, ID Register 12
D10.40 TRCIDR13, ID Register 13
D10.41 TRCIMSPEC0, Implementation Specific Register 0
D10.42 TRCITATBIDR, Integration ATB Identification Register
D10.43 TRCITCTRL, Integration Mode Control Register
D10.44 TRCITIATBINR, Integration Instruction ATB In Register
D10.45 TRCITIATBOUTR, Integration Instruction ATB Out Register
D10.46 TRCITIDATAR, Integration Instruction ATB Data Register
D10.47 TRCLAR, Software Lock Access Register
D10.48 TRCLSR, Software Lock Status Register
D10.49 TRCCNTVRn, Counter Value Registers 0-1
D10.50 TRCOSLAR, OS Lock Access Register
D10.51 TRCOSLSR, OS Lock Status Register
D10.52 TRCPDCR, Power Down Control Register
D10.53 TRCPDSR, Power Down Status Register
D10.54 TRCPIDR0, ETM Peripheral Identification Register 0
D10.55 TRCPIDR1, ETM Peripheral Identification Register 1
D10.56 TRCPIDR2, ETM Peripheral Identification Register 2
D10.57 TRCPIDR3, ETM Peripheral Identification Register 3
D10.58 TRCPIDR4, ETM Peripheral Identification Register 4
D10.59 TRCPIDRn, ETM Peripheral Identification Registers 5-7
D10.60 TRCPRGCTLR, Programming Control Register
D10.61 TRCRSCTLRn, Resource Selection Control Registers 2-16
D10.62 TRCSEQEVRn, Sequencer State Transition Control Registers 0-2
D10.63 TRCSEQRSTEVR, Sequencer Reset Control Register
D10.64 TRCSEQSTR, Sequencer State Register
D10.65 TRCSSCCR0, Single-Shot Comparator Control Register 0
D10.66 TRCSSCSR0, Single-Shot Comparator Status Register 0
D10.67 TRCSTALLCTLR, Stall Control Register
D10.68 TRCSTATR, Status Register
D10.69 TRCSYNCPR, Synchronization Period Register
D10.70 TRCTRACEIDR, Trace ID Register
D10.71 TRCTSCTLR, Global Timestamp Control Register
D10.72 TRCVICTLR, ViewInst Main Control Register
D10.73 TRCVIIECTLR, ViewInst Include-Exclude Control Register
D10.74 TRCVISSCTLR, ViewInst Start-Stop Control Register
D10.75 TRCVMIDCVR0, VMID Comparator Value Register 0
D10.76 TRCVMIDCCTLR0, Virtual context identifier Comparator Control Register 0
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