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The GIC CPU Interface is always implemented within the Cortex®‑A76 core.
However, you can disable it if you assert the GICCDISABLE signal HIGH at reset. If you disable the GIC CPU interface, the input pins nVIRQ and nVFIQ can be driven by an external GIC in the SoC. GIC system register access generates UNDEFINED instruction exceptions when the GICCDISABLE signal is HIGH.
If the GIC is enabled, the input pins nVIRQ and nVFIQ must be tied off to HIGH. This is because the internal GIC CPU interface generates the virtual interrupt signals to the cores. The nIRQ and nFIQ signals are controlled by software, therefore there is no requirement to tie them HIGH.