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The memory region attributes specified in the TLB entry, or in the descriptor in case of translation table walk, determine if the access is:
|Device-nGnRnE||Device non-Gathering, non-Reordering, No Early Write Acknowledgment.|
|Device-nGnRE||Device non-Gathering, non-Reordering, Early Write Acknowledgment.|
|Device-nGRE||Device non-Gathering, Reordering, Early Write Acknowledgment.|
|Device-GRE||Device Gathering, Reordering, Early Write Acknowledgment.|
In the Cortex®‑A76 core, a page is cacheable only if the inner memory attribute and outer memory attribute are Write Back. In all other cases, all pages are downgraded to Non-cacheable Normal memory.
When the MMU is disabled at stage 1 and stage 2, and SCTLR.I is set to 1, instruction prefetches are cached in the instruction cache but not in the unified cache. In all other cases, normal behavior on memory attribute applies.
See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information on translation table formats.