B2.22 AVTCR_EL2, Auxiliary Virtualized Translation Control Register, EL2

The AVTCR_EL2 determines the values of PBHA on stage 2 page table walks memory access in EL1 Non-secure translation regime if stage 2 is enable.

This register is only used when Page Based Hardware Attributes (PBHA) is configured by the core.

Bit field descriptions

AVTCR_EL2 is a 64-bit register.

Figure B2-17 AVTCR_EL2 bit assignments
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[63:10]
RES0.
HWVAL60, [9]
Indicates the value of PBHA[1] page table walks memory access if HWEN60 is set.
HWVAL59, [8]
Indicates the value of PBHA[1] page table walks memory access if HWEN59 is set.
[7:2]
RES0.
HWEN60, [1]
Enables PBHA[1] page table walks memory access. If this bit is clear, PBHA[1] on page table walks is 0.
HWEN59, [0]
Enables PBHA[0] page table walks memory access. If this bit is clear, PBHA[0] on page table walks is 0.
Configurations

AArch64 register AVTCR_EL2 is architecturally mapped to AArch32 register AVTCR.

Usage constraints

Accessing the AVTCR_EL2

To access the AVTCR_EL2:

MRS  Xt , S< 3  4  c15  c7  1> ; Read AVTCR_EL2 into Xt   
MSR S < 3   4  c15   c7  1 > , Xt   ; Write Xt to AVTCR_EL2

This syntax is encoded with the following settings in the instruction encoding:

Op0 Op1 CRn CRm Op2
3 4 c15 c7 1
Accessibility

AVTCR_EL2 is accessible as follows:

EL0 EL1 (NS) EL1 (S) EL2 EL3 (SCR.NS=1) EL3 (SCR.NS=0)
- - - RW RW RW
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