A1.4 Supported standards and specifications

The Cortex®‑A76 core implements the Arm®v8‑A architecture and some architecture extensions. It also supports interconnect, interrupt, timer, debug, and trace architectures.

Table A1-2 Compliance with standards and specifications

Architecture specification or standard Version Notes
Arm architecture


  • AArch32 execution state at Exception level EL0 only. AArch64 execution state at all Exception levels (EL0-EL3).
  • A64, A32, and T32 instruction sets.
Arm architecture extensions
  • Armv8.1‑A extensions
  • Armv8.2‑A extensions
  • Cryptographic extension

  • RAS extension
  • Armv8.3‑A extensions
  • Armv8.4‑A dot product instructions
  • Armv8.5‑A extensions
  • The Cortex‑A76 core implements the LDAPR instructions introduced in the Armv8.3‑A extensions.
  • The Cortex‑A76 core implements the SDOT and UDOT instructions introduced in the Armv8.4‑A extensions.
  • The Cortex‑A76 core implements the PSTATE Speculative Store Bypass Safe (SSBS) bit introduced in the Armv8.5‑A extension.
Generic Interrupt Controller GICv4 -
Generic Timer Armv8‑A 64-bit external system counter with timers within each core.
Debug Armv8‑A With support for the debug features added by the Armv8.2‑A extensions.
CoreSight CoreSightv3 -
Embedded Trace Macrocell ETMv4.2 Instruction trace only.

See Additional reading for a list of architectural references.

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