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The Cortex®‑A76 core implements the GIC CPU interface as described in the Arm® Generic Interrupt Controller Architecture Specification.
This interfaces with an external GICv3 or GICv4 distributor component within the cluster system and is a resource for supporting and managing interrupts. The GIC CPU interface hosts registers to mask, identify and control states of interrupts forwarded to that core. Each core in the cluster system has a GIC CPU interface component and connects to a common external distributor component.
The GICv4 architecture supports:
The GIC includes interrupt grouping functionality that supports:
This chapter describes only features that are specific to the Cortex‑A76 core implementation.