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The Cortex®‑A76 core is an Armv8 compliant core that supports execution in AArch64 state.
The following table shows the AArch64 behavior.
Table A5-2 AArch64 behavior
|Address translation system||The Armv8 address translation system resembles an extension to the Long descriptor format address translation system to support the expanded virtual and physical address space.|
|Translation granule||4KB, 16KB, or 64KB for Armv8 Virtual Memory System Architecture (VMSA)|
|ASID size||8 or 16 bits depending on the value of TCR_ELx.AS.|
|VMID size||8 or 16 bits depending on the value of VTCR_EL2.VS.|
Maximum 40 bits.
Any configuration of TCR_ELx.IPS over 40 bits is considered as 40 bits. You can enable or disable each stage of the address translation independently.
The Cortex‑A76 core also supports the Virtualization Host Extension (VHE) including ASID space for EL2. When VHE is implemented and enabled, EL2 has the same behavior as EL1.
See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for more information on concatenated translation tables and for address translation formats.