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The following table summarizes the 32-bit and 64-bit debug control registers that are accessible in the AArch32 Execution state from the internal CP14 interface. These registers are accessed by the
MRC instructions in the order of CRn, op2, CRm, Op1 or
MRRC instructions in the order of CRm, Op1.
For those registers not described in this chapter, see the Arm® Architecture Reference Manual Arm®v8, for Arm®v8-A architecture profile.
Table D1-1 AArch32 debug register summary
||Debug Status and Control Register, Internal View|
|c0||0||c5||0||DBGDTRTXint||WO||-||Debug Data Transfer Register, Transmit, Internal View|
||Debug Data Transfer Register, Receive, Internal View|