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The Cortex®‑A76 core supports fault injection for the purpose of testing fault handling software.
The core is programmable to inject an error for any of the possible error types (corrected error, deferred error, uncontainable error, and recoverable error) on a future memory access. When that access is performed, the core responds as if an error was detected on that access by asserting error interrupts, logging information in the error records, and taking aborts as appropriate for the type of error. Injecting an error will not affect the data in the RAM or the checking process itself. When a real error is detected on an access for which an injected error is programmed, the injected error will not prevent the core from handling the real error. The RAS register might log the injected error or the real error in this case.
To get the error injection to work:
The following table describes all the possible types of error that the core can encounter and therefore inject.
Table A8-3 Errors injected in the Cortex‑A76 core
|Corrected errors||A CE is generated for a single-bit ECC error on L1 data caches and L2 caches, both on data and tag RAMs.|
|Deferred errors||A DE is generated for a double-bit ECC error on L1 data caches and L2 caches, but only on data RAM.|
|Uncontainable errors||A UC is generated for a double-bit ECC error on L1 data caches and L2 caches, but only on tag RAM.|
The following table describes the registers that handle error injection in the Cortex‑A76 core.
Table A8-4 Error injection registers
|ERR0PFGF_EL1||The ERR Pseudo Fault Generation Feature register defines which errors can be injected.|
|ERR0PFGCTL_EL1||The ERR Pseudo Fault Generation Control register controls the errors that are injected.|
|ERR0PFGCDN_EL1||The ERR Pseudo Fault Generation Count Down register controls the fault injection timing.|