9 Control Status Word register, CSW

The CSW register configures and controls accesses through the AXI master interface to the connected memory system.

The CSW register characteristics are:

Attributes
Offset

0x0D00

Type

Read-write

Reset

0x30-060-2

Width

32

The following figure shows the bit assignments.

Figure 9-88 CSW register bit assignments
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The following table shows the bit assignments.

Table 9-92 CSW register bit assignments

Bits Reset value Name Function
[31] 0b0 RAZ/WI

Read-As-Zero, Writes Ignored.

[30:28] 0b011 Prot

Drives AXI master interface ports arprot_m[2:0] and awprot_m[2:0] which specifies the AXI4 protection encoding. The reset value is 0x3 (Data, Non-secure, Privileged). Together with authentication interface signals CSW[1] determines whether a secure access is allowed on the master interface as follows, access = dbgen && spiden || dbgen && CSW[1].

[27:24] 0b0000 Cache

Specifies the AXI3 and AXI4 cache encodings. Software must never program an invalid combination of values in CSW.Cache and CSW.Domain fields. The software must use different cache encoding values for reads and writes. If an illegal set of cache and domain values is programmed, the AXI AP does not issue the transaction on its master interface and generates a memory access error.

[23] UNKNOWN SDeviceEn

Indicates the status of the spiden and spniden ports. It is set when either spiden or spniden is HIGH, and remains clear otherwise. If this bit is clear, Secure AXI transfers are not permitted. Non-secure memory accesses and internal register accesses that do not initiate memory accesses are permitted regardless of the status of this bit.

[22:18] 0b00000 RAZ/WI

Read-As-Zero, Writes Ignored.

[17] 0b0 ERRSTOP

Stop on error.

0

Memory access errors do not prevent future memory accesses.

1

Memory access errors prevent future memory accesses.

[16] 0b0 ERRNPASS

Errors that are not passed upstream.

0

Memory access errors that are passed upstream.

1

Memory access errors that are not passed upstream.

[15] 0b0 RAZ/WI

Read-As-Zero, Writes Ignored.

[14:13] 0b11 Domain

Shareable transaction encoding for ACE.

0x0

Non-shareable.

0x1

Shareable, inner domain, includes additional masters.

0x2

Shareable, outer domain, also includes inner or additional masters.

0x3

Shareable, system domain, all masters included.

[12] 0b0 ACEEnable

Enable ACE transactions, including barriers.

0

Disable

1

Enable

[11:8] 0b0000 Mode

Specifies the mode of operation.

0x0

Normal download or upload mode.

0x1

Barrier transaction.

0x2

Reserved.

0x3

Reserved.

0x4

Reserved.

0x5

Reserved.

0x6

Reserved.

0x7

Reserved.

0x8

Reserved.

0x9

Reserved.

0xA

Reserved.

0xB

Reserved.

0xC

Reserved.

0xD

Reserved.

0xE

Reserved.

0xF

Reserved.

[7] 0b0 TrInProg

Transfer in progress. This field indicates whether a transfer is in progress on the AXI master interface.

[6] UNKNOWN DeviceEn

Indicates the status of dbgen and niden ports. The bit is set when either dbgen or niden is high, and is clear otherwise. If this bit is clear, no AXI transfers are carried out, that is, both secure and non-secure accesses are blocked).

[5:4] 0b00 AddrInc

Auto address increment mode on RW data access. Only increments if the current transaction completes without an error response and the transaction is not aborted.

0x0

Auto increment OFF.

0x1

Increment, single. Single transfer from corresponding byte lane.

0x2

Reserved.

0x3

Reserved.

[3] 0b0 RAZ/WI

Read-As-Zero, Writes Ignored.

[2:0] 0b010 Size

Size of the data access to perform.

0x0

8 bits.

0x1

16 bits.

0x2

32 bits.

0x3

64 bits, if LDE is supported, Reserved, if LDE is not supported.

0x4

Reserved.

0x5

Reserved.

0x6

Reserved.

0x7

Reserved.

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