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css600_jtagap provides JTAG access to on-chip components, operating as a JTAG master port to drive JTAG chains throughout a SoC.
The JTAG command protocol is byte-oriented, with a word wrapper on the read and write ports to yield acceptable performance from the 32-bit internal data bus in the DAP. Daisy chaining is avoided by using a port multiplexer. These two features prevent slower cores from impeding faster cores.
The following figure shows the external connections on the JTAG Access Port.
See the Arm® Debug Interface Architecture Specification ADIv6.0 for more information.