8 Cortex-A5 PIL overview

A description of the Cortex®‑A5 Processor Integration Layer (PIL).

The Cortex‑A5 PIL provides a configurable example integration of the processor and several tightly coupled debug components.

The Cortex‑A5 PIL is configurable and consists of the following:

The Cortex‑A5 PIL has the following interfaces:

The following figure shows a block diagram of the Cortex‑A5.

Figure 8-1 Cortex‑A5 PIL block diagram
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This section contains the following subsections:
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