The Cortex‑A5 PIL provides a configurable example integration of the processor and several tightly coupled debug components.

The Cortex‑A5 PIL is configurable and consists of the following:

• A ROM table.
• An APB subsystem.
• A Cross Trigger Matrix (CTM).
• Logic that enables sharing an ETM trace unit between several processors.
• Zero to four Cross Trigger Interfaces (CTIs), referred to as CTI0, CTI1, CTI2, and CTI3.
• Zero to four Embedded Trace Macrocell (ETM) trace units, referred to as ETM0, ETM1, ETM2, and ETM3.
• A Cortex‑A5 uniprocessor, referred to as Processor0, or a Cortex-A5 MPCore processor with up to four processors, referred to as Processor0, Processor1, Processor2, and Processor3.

The Cortex‑A5 PIL has the following interfaces:

• APB debug.
• A CTI channel.
• Zero to four ATB trace outputs.
• One or two AXI interfaces for connection to the memory system.
• Accelerator Coherency Port (ACP) to provide memory coherency between each processor in the Cortex‑A5 PIL and an external master.

The following figure shows a block diagram of the Cortex‑A5.