2 Additional AXI error responses

The AXI-AP produces error responses for AXI-initiated and AP-initiated transfers.

AXI initiated error responses

An error response that is received on the AXI master interface propagates onto the Debug APB bus as the transfer is completed.

For 64-bit data transfer, a sequence of two reads or writes must be generated on the Debug APB bus for a single 64-bit access on the AXI interface. For reads, the first read request on the Debug APB bus sends a read request on the AXI interface. For writes, a write access is sent on the AXI interface only after two write requests are received on the Debug APB bus.

Therefore, an error response that is received for a read request is for the first read request on the Debug APB bus while an error response that is received for a write request is for the second write request on the Debug APB bus.

AP-initiated error response

AXI-AP reads after a 64-bit AXI read sequence is broken

Read requests from the Debug APB bus must access both BDx registers, or a consecutive pair of DAR registers forming an aligned 64-bit address. Read requests must access the lower-numbered register first. For a DRW register access, two read requests are required to get the entire 64-bit word from the AXI interface.

All other accesses, such as a read followed by a write access to the same or different registers, return an error response to the DP.

AXI-AP writes after a 64-bit write sequence is broken

Write requests from the Debug APB interface must access both BDx registers of the pair, or consecutive DAR registers forming an aligned 64-bit address, and must access the lower-numbered register first. For a DRW register access, two write requests are required to build a 64-bit packet as write data on the AXI interface.

All other accesses, such as a write followed by another read-write access to different registers, return an error response.

For example, after accessing the DRW register, the next access on the Debug APB bus must be a write to the DRW register. Any other access returns an error response.

Similarly, after accessing BD0, the next access must be a write to BD1. Any other access returns an error response.

Aborted AXI barrier transactionIt is possible to abort a barrier transaction that has not yet completed. When the abort request is generated, the Debug APB transaction is completed in the next cycle. However the CSW.TrInPrg bit remains set to indicate that the AXI interface is busy waiting to complete the transaction. While the AXI interface is busy, a read-write request to DRW, DAR, or BDx registers that results in a transaction on the AXI interface, causes the AXI-AP to return an error response to the DP.
Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.