8 Cortex-M3 PIL overview
The Cortex®-M3 Processor Integration Layer (PIL) consists of the following:
- A processor that has an Instrumentation Trace
Macrocell (ITM) and Advanced High-performance Bus
(AHB)-Access Port (AP).
- An optional Wakeup Interrupt Controller (WIC).
- A ROM table that connects to the processor through a Private Peripheral Bus (PPB).
- An Embedded Trace Macrocell (ETM) trace unit that connects to the processor.
- A CTI for debug event communication.
The Cortex‑M3 PIL supports the following external interfaces:
- Two Advanced Trace Bus (ATB) interfaces that connect to the CoreSight™ subsystem.
- An Advanced Peripheral Bus (APB) interface
for adding debug components to the PPB.
- An APB interface that connects to the debug port in the CoreSight subsystem.
- Processor-specific signals such as interrupt signals, system control
signals, and status signals.
The following figure shows a block diagram of the Cortex‑M3 PIL.
8-7 Cortex-M3 PIL block diagram
This section contains the following subsections: