9 Input Address High register, INADDRHI

This register, together with the INADDRLO register, enables the CATU to validate the input address on the AXI slave interface. It gives the upper 32 bits of the lower value of the valid input address range. Software must program the INADDRHI register with an initial value before setting CONTROL.ENABLE bit to 1. It is writable only when CONTROL.ENABLE is clear and STATUS.READY is set.

The INADDRHI register characteristics are:

Attributes
Offset

0x002C

Type

Read-write

Reset

0x--------

Width

32

The following figure shows the bit assignments.

Figure 9-490 INADDRHI register bit assignments
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The following table shows the bit assignments.

Table 9-506 INADDRHI register bit assignments

Bits Reset value Name Function
[31:8] UNKNOWN RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[7:0] UNKNOWN INADDRHI

Holds the upper bits, that is, bit[32] and above, of the lower value of the valid AXI address range.

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