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This register, together with the INADDRLO register, enables the CATU to validate the input address on the AXI slave interface. It gives the upper 32 bits of the lower value of the valid input address range. Software must program the INADDRHI register with an initial value before setting CONTROL.ENABLE bit to 1. It is writable only when CONTROL.ENABLE is clear and STATUS.READY is set.
The INADDRHI register characteristics are:
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-506 INADDRHI register bit assignments
Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.
Holds the upper bits, that is, bit and above, of the lower value of the valid AXI address range.