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The narrow timestamp asynchronous bridge supports two power domains.
Q-Channel Low Power interfaces are provided to ensure that:
When a low-power request is issued to the bridge by driving pwr_qreq_n LOW, the bridge:
When a powerup request is issued to the bridge by driving pwr_qreq_n HIGH, the bridge sends a resynchronization event through the narrow timestamp master interface so that downstream components synchronize to the correct timestamp value.
The bridge does not implement an automatic wake and therefore does not have a qactive signal on the power LPI. It always accepts requests to power down.
Each clock has an LPI for managing power reduction using high-level clock gating. If other components in the same part of the timestamp network are clock gated, the bridge can also be independently clock gated.
Before gating a clock, the clk_s_qreq_n, or clk_m_qreq_n, signal must be asserted LOW and the clock controller must wait for clk_s_qaccept_n, or clk_m_qaccept_n, to go LOW. While clock gated, the bridge ignores all timestamp packets arriving on the slave interface. If a request is made for a power state change using pwr_qreq_n to power the master side up or down, then the clock is requested using the clk_s_qactive signal.
For more information on the Low-power features, see the AMBA® Low Power Interface Specification, Arm® Q‑Channel and P‑Channel Interfaces.