Arm CoreSight System-on-Chip SoC-600 Technical Reference Manual : About this book

Product revision status

The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2, where:

r`m`	Identifies the major revision of the product, for example, r1.
p`n`	Identifies the minor revision or modification status of the product, for example, p2.

Intended audience

This book is written for the following audiences:

Hardware and software engineers who want to incorporate CoreSight™ SoC-600 into their design and produce real-time instruction and data trace information from a SoC.
Software engineers writing tools to use CoreSight SoC-600.

This book assumes that readers are familiar with AMBA^® bus design and JTAG methodology.

Using this book

This book is organized into the following chapters:

Chapter 1 Introduction: This chapter introduces the CoreSight™ SoC-600.
Chapter 2 DAP components functional description: This chapter describes the functionality of the SoC-600.
Chapter 3 APB infrastructure components functional description: This chapter describes the functionality of the APB infrastructure components.
Chapter 4 ATB infrastructure components functional description: This chapter describes the functionality of the ATB infrastructure components.
Chapter 5 Timestamp components functional description: This chapter describes the functionality of the timestamp components.
Chapter 6 Embedded Cross Trigger components functional description: This chapter describes the functionality of the Embedded Cross Trigger (ECT) components.
Chapter 7 Authentication components functional description: This chapter describes the functionality of the authentication components.
Chapter 8 Processor Integration Layer components: This chapter gives an overview of the Cortex^® Processor Integration Layers (PILs).
Chapter 9 Programmers model: This chapter describes the programmers models for all CoreSight™ SoC-600 components that have programmable registers.
Appendix A Revisions: This appendix describes the technical changes between released issues of this book.

Glossary

The Arm^® Glossary is a list of terms used in Arm documentation, together with definitions for those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning.

See the Arm^® Glossary for more information.

Typographic conventions

italic

Introduces special terminology, denotes cross-references, and citations.

bold

Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate.

monospace

Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code.

monospace

Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name.

monospace italic

Denotes arguments to monospace text where the argument is to be replaced by a specific value.

monospace bold

Denotes language keywords when used outside example code.

<and>

Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example:

MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>

SMALL CAPITALS

Used in body text for a few terms that have specific technical meanings, that are defined in the Arm^® Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.

Timing diagrams

The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.

Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.

Figure 1 Key to timing diagram conventions

Signals

The signal conventions are:

Signal level

The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:

HIGH for active-HIGH signals.
LOW for active-LOW signals.

Lowercase n

At the start or end of a signal name denotes an active-LOW signal.

Additional reading

This book contains information that is specific to this product. See the following documents for other relevant information.

Arm publications

This book contains information that is specific to this product. See the following documents for other relevant information:

Arm^® CoreSight™ Architecture Specification v3.0 (ARM IHI 0029).
Arm^® AMBA^® APB Protocol Specification Version 2.0 (ARM IHI 0024).
Arm^® AMBA^® AXI and ACE Protocol Specification (ARM IHI 0022).
Arm^® AMBA^® 4 ATB Protocol Specification (ARM IHI 0032).
Arm^® AMBA^® 5 AHB Protocol Specification AHB5, AHB-Lite (ARM IHI 0033).
Arm^® Debug Interface Architecture Specification ADIv6.0 (ARM IHI 0074).
Arm^® AMBA^® 4 AXI4-Stream Protocol Specification (ARM IHI 0051
Arm^® CoreLink™ LPD-500 Low Power Distributor Technical Reference Manual (ARM 100361).
AMBA^® Low Power Interface Specification, Arm^® Q‑Channel and P‑Channel Interfaces (ARM IHI 0068).
Arm^® Architecture Reference Manual ARMv7-A and ARMv7-R edition (ARM DDI 0406).
Arm^® Architecture Reference Manual ARMv8, for ARMv8‑A architecture profile (ARM DDI 0487).
Arm^® Embedded Trace Macrocell Architecture Specification ETMv4.0 to ETMv4.3 (ARM IHI 0064)
Arm^® CoreSight™ Program Flow Trace Architecture Specification PFTv1.0 and PFTv1.1 (ARM IHI 0035).

The following confidential books are only available to licensees:

Arm^® CoreSight™ SoC-600 Configuration and Integration Manual (ARM 100807).
Arm^® CoreSight™ SoC-600 User Guide (ARM 101128).
Arm^® Socrates™ System Builder Installation Guide (ARM 100329).
Arm^® Cortex^®-M3 Integration and Implementation Manual (ARM DII 0240).
Arm^® Cortex^®-M4 Integration and Implementation Manual (ARM DII 0239).
Arm^® Power Control System Architecture Specification Version 1.0 (ARM DEN 0050).

Other publications

Verilog-2001 Standard (IEEE Std 1364-2001).
Accellera, IP-XACT version 1685-2009.
IEEE 1149.1-2001 IEEE Standard Test Access Port and Boundary Scan Architecture (JTAG).

Non-Confidential	PDF version	100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.