2 Debug Port

The css600_dp module implements the JTAG and Serial Wire Debug Port protocols, either of which can be omitted to save area in systems that do not require both protocols.

The debug port communicates with the debug components through the APB infrastructure that is connected to the debug port APB master interface.

The debug port implements the following features:

  • ADIv6 architecture.
  • Single clock domain in each part.
  • Asynchronous bridge between the slave and master parts.
  • 4-bit or 8-bit Instruction register for JTAG implementation.
  • Separate slave and master components, implementing JTAG, Serial Wire, or both in the slave, and APB in the master.

The following figure shows the external connections on the Debug Port.

Figure 2-1 css600_dp logical connections
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