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Integration test to view channel events. The integration test register includes a latch that is set when a pulse is received on a channel input. When read, a register bit reads as 1 if the channel has received a pulse since it was last read. The act of reading the register automatically clears the 1 to a 0. When performing integration testing it is therefore important to coordinate the setting of event latches and reading/clearing them.
The ITCHIN register characteristics are:
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-585 ITCHIN register bit assignments
Software should write the field as all 0s.
Reads the latched value of the channel inputs.