9 Integration Test Channel Input register, ITCHIN

Integration test to view channel events. The integration test register includes a latch that is set when a pulse is received on a channel input. When read, a register bit reads as 1 if the channel has received a pulse since it was last read. The act of reading the register automatically clears the 1 to a 0. When performing integration testing it is therefore important to coordinate the setting of event latches and reading/clearing them.

The ITCHIN register characteristics are:

Attributes
Offset

0x0EF4

Type

Read-only

Reset

0x00000000

Width

32

The following figure shows the bit assignments.

Figure 9-566 ITCHIN register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 9-585 ITCHIN register bit assignments

Bits Reset value Name Function
[31:4] 0x0 SBZ

Software should write the field as all 0s.

[3:0] 0b0000 CTICHIN

Reads the latched value of the channel inputs.

Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.