9 AXI control register, AXICTRL

This register controls the CATU scatter list read accesses to system memory through the AXI interface. It is writable only when CONTROL.ENABLE is clear and STATUS.READY is set.

The AXICTRL register characteristics are:

Attributes
Offset

0x0008

Type

Read-write

Reset

0x000000--

Width

32

The following figure shows the bit assignments.

Figure 9-485 AXICTRL register bit assignments
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The following table shows the bit assignments.

Table 9-501 AXICTRL register bit assignments

Bits Reset value Name Function
[31:8] 0x0 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[7:4] UNKNOWN ARCACHE

This field controls the AXI cache encoding, that is, the value that is driven on AXI master bus arcache_m[3:0], for scatter list read transfers. Software must only program a valid AXI3 or AXI4 cache encoding value in this field.

[3:2] 0b00 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[1:0] UNKNOWN ARPROT

Secure Access, Privileged Access. This field controls the value that is driven on arprot_m[1:0] on the AXI master interface during scatter list read transfers. The CATU only performs data accesses, so the arprot_m[2] outputs are LOW for all AXI transfers.

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