8 Cortex-M0 PIL overview
The Cortex®‑M0 Processor Integration Layer (PIL) consists of the following:
- A Cortex‑M0 processor.
- An optional Wake up Interrupt Controller
- A ROM table to identify the PIL contents.
- A Cross Trigger Interface (CTI) for debug
The Cortex‑M0 PIL has the following interfaces:
- An AHB-Lite master interface that connects to the system Network Interconnect (NIC).
- An AHB slave interface that connects to the AHB-AP port of the CoreSight™ DAP.
- An AHB slave interface for accessing the CTI and ROM table.
- Processor-specific signals such as interrupt signals, system control
signals, and status signals.
The following figure shows a block diagram of the Cortex‑M0.
8-6 Cortex‑M0 PIL block diagram
This section contains the following subsections: