9 Register summary

The following table shows the registers in offset order from the base memory address.

Note:

A reset value containing one or more '-' means that this register contains UNKNOWN or IMPLEMENTATION-DEFINED values. See the relevant register description for more information.

Locations that are not listed in the table are Reserved.

Table 9-290 css600_tmc_etb - APB4_Slave_0 register summary

Offset

Name

Type

Reset

Width

Description

0x0004

RSZ

RW

0x0000008-

32

RAM Size register, RSZ

0x000C

STS

RW

0x000000--

32

Status register, STS

0x0010

RRD

RO

0x--------

32

RAM Read Data register, RRD

0x0014

RRP

RW

0x00000---

32

RAM Read Pointer register, RRP

0x0018

RWP

RW

0x00000---

32

RAM Write Pointer register, RWP

0x001C

TRG

RW

0x000000--

32

Trigger Counter register, TRG

0x0020

CTL

RW

0x00000000

32

Control Register, CTL

0x0024

RWD

WO

0x00000000

32

RAM Write Data register, RWD

0x0028

MODE

RW

0x0000000-

32

Mode register, MODE

0x002C

LBUFLEVEL

RO

0x000000--

32

Latched Buffer Fill Level, LBUFLEVEL

0x0030

CBUFLEVEL

RO

0x000000--

32

Current Buffer Fill Level, CBUFLEVEL

0x0034

BUFWM

RW

0x000000--

32

Buffer Level Water Mark, BUFWM

0x0300

FFSR

RO

0x0000000-

32

Formatter and Flush Status Register, FFSR

0x0304

FFCR

RW

0x00000000

32

Formatter and Flush Control Register, FFCR

0x0308

PSCR

RW

0x0000000A

32

Periodic Synchronization Counter Register, PSCR

0x0EE0

ITEVTINTR

WO

0x00000000

32

Integration Test Event and Interrupt Control Register, ITEVTINTR

0x0EE8

ITTRFLIN

RO

0x00000000

32

Integration Test Trigger In and Flush In register, ITTRFLIN

0x0EEC

ITATBDATA0

RO

0x00000000

32

Integration Test ATB Data 0 Register, ITATBDATA0

0x0EF0

ITATBCTR2

WO

0x00000000

32

Integration Test ATB Control 2 Register, ITATBCTR2

0x0EF4

ITATBCTR1

RO

0x00000000

32

Integration Test ATB Control 1 Register, ITATBCTR1

0x0EF8

ITATBCTR0

RO

0x00000000

32

Integration Test ATB Control 0 Register, ITATBCTR0

0x0F00

ITCTRL

RW

0x00000000

32

Integration Mode Control Register, ITCTRL

0x0FA0

CLAIMSET

RW

0x0000000F

32

Claim Tag Set Register, CLAIMSET

0x0FA4

CLAIMCLR

RW

0x00000000

32

Claim Tag Clear Register, CLAIMCLR

0x0FB8

AUTHSTATUS

RO

0x00000000

32

Authentication Status Register, AUTHSTATUS

0x0FC4

DEVID1

RO

0x00000001

32

Device Configuration Register 1, DEVID1

0x0FC8

DEVID

RO

0x00000-00

32

Device Configuration Register, DEVID

0x0FCC

DEVTYPE

RO

0x00000021

32

Device Type Identifier Register, DEVTYPE

0x0FD0

PIDR4

RO

0x00000004

32

Peripheral Identification Register 4, PIDR4

0x0FD4

PIDR5

RO

0x00000000

32

Peripheral Identification Register 5, PIDR5

0x0FD8

PIDR6

RO

0x00000000

32

Peripheral Identification Register 6, PIDR6

0x0FDC

PIDR7

RO

0x00000000

32

Peripheral Identification Register 7, PIDR7

0x0FE0

PIDR0

RO

0x000000E9

32

Peripheral Identification Register 0, PIDR0

0x0FE4

PIDR1

RO

0x000000B9

32

Peripheral Identification Register 1, PIDR1

0x0FE8

PIDR2

RO

0x0000003B

32

Peripheral Identification Register 2, PIDR2

0x0FEC

PIDR3

RO

0x00000000

32

Peripheral Identification Register 3, PIDR3

0x0FF0

CIDR0

RO

0x0000000D

32

Component Identification Register 0, CIDR0

0x0FF4

CIDR1

RO

0x00000090

32

Component Identification Register 1, CIDR1

0x0FF8

CIDR2

RO

0x00000005

32

Component Identification Register 2, CIDR2

0x0FFC

CIDR3

RO

0x000000B1

32

Component Identification Register 3, CIDR3

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