4.4 Alternating FF/00 pattern

On each clock cycle, the tracedata pins are either all set FF pattern or all cleared 00 pattern.

The pattern is effectively 64 bits wide, with bits[63:32] = 0xFFFFFFFF and bits[31:0] = 0x00000000.

The Current Port Size Register (CSPSR) sets the width of tracedata (tracedata-width). When pattern generation starts, tracedata[0] is aligned with the 64-bit pattern bit[0] and tracedata-width bits of the pattern are output on tracedata[tracedata-width-1:0]. On the next rising edge of traceclk, the pattern is shifted to the right by the width of tracedata. The next tracedata-width pattern bits, starting at bit[tracedata-width], then outputs on tracedata. This sequence is repeated until all 64 bits of the pattern are consumed, at which point the pattern repeats.

Example 1 - tracedata is 8 bits wide.

Figure 4-20 Example 8-bit FF/00 tracedata pattern
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In this example, the tracedata width is 8 bits. As the 8-bit tracedata width is a convenient fraction of the 64-bit repeating pattern, tracedata takes the values 00, 00, 00, 00, FF, FF... as the pattern is shifted right.

Example 2 - tracedata is 5 bits wide.

Figure 4-21 Example 5-bit FF/00 tracedata pattern
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In this example, the tracedata width is 5 bits. This time, tracedata does not follow the corresponding pattern byte values. The tracedata values are 00, 00, 00, 00, 00, 00, 1C, 1F...

This sequence of alternating the entire set of data pins is a good way to check the power supply stability to the TPIU and the final pads, because of the stresses the drivers are under.

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