9 Configuration register, CFG

This is the AXIAP Configuration register.

The CFG register characteristics are:

Attributes
Offset

0x0DF4

Type

Read-only

Reset

0x000101A-

Width

32

The following figure shows the bit assignments.

Figure 9-97 CFG register bit assignments
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The following table shows the bit assignments.

Table 9-101 CFG register bit assignments

Bits Reset value Name Function
[31:20] 0b000000000000 RAZ/WI

Read-As-Zero, Writes Ignored.

[19:16] 0b0001 TARINC

TAR incrementer size. Returns 0x1 indicating a TAR incrementer size of 10-bits.

[15:12] 0b0000 RAZ/WI

Read-As-Zero, Writes Ignored.

[11:8] 0b0001 ERR

Error functionality implemented. Returns 0x1 indicating that Error Response Handling version 1 is implemented.

[7:4] 0b1010 DARSIZE

Size of DAR register space. Returns 0xA indicating that 1KB (256 registers, each 32-bit wide) of DAR is implemented.

[3] 0b0 RAZ/WI

Read-As-Zero, Writes Ignored.

[2] IMPLEMENTATION_DEFINED LD

Large Data. Indicates support for LDE (data items greater than 32 bits). This value of bit is fixed in a given configuration of AXI AP based on parameter AXI_DATA_WIDTH.

0

Only 8, 16, and 32-bit data items are supported.

1

Support for 64-bit data item in addition to 8, 16, and 32-bit data.

[1] IMPLEMENTATION_DEFINED LA

Long Address. Indicates support for LAE (greater than 32-bit of addressing). This bit value is fixed in a given configuration of AXI AP based on parameter AXI_ADDR_WIDTH.

0

32 or fewer bits of addressing. Registers 0xD08 and 0xDF0 are reserved.

1

64 or fewer bits of addressing. TAR and BASE registers occupy two locations, at 0xD04 and 0xD08, and at 0xDF8 and 0xDF0 respectively.

[0] 0b0 BE

Big-endian. Always read as 0 because AXI AP only supports little-endian.

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