2 AXI-AP features

The AXI-AP implements the following features:

  • Error response.
  • Stalling accesses.
  • Little endian only.
  • Single clock domain.
  • AXI4 interface support.
  • Auto-incrementing TAR.
  • 8, 16, 32, or 64 bits data access.
  • 32 or 64 bits Large Physical Address (LPA) extension support.
  • AXI transfers:
    • Burst size of 1 only.
    • Write and read transfers.
    • No out-of-order transactions.
    • No multiple outstanding accesses.
    • Only aligned transfers are supported.
  • ACE-Lite:
    • Barrier transactions.
    • All transactions to Non-shareable memory regions.
    • For reads only - only supports the ReadOnce transaction type.
    • For writes only - only supports the WriteUnique transaction type.
    • Limited subset of transactions to shareable memory regions.
    • Limited set of commands to support coherency in the system.
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