8 Cortex®‑A5 PIL debug memory map

The debug components in the Cortex®‑A5 PIL share memory space with the processor system.

paddrdbg[31] is inverted and mapped to paddrdbg[17] inside the PIL. The following tables show the locations of the Cortex‑A5 PIL CoreSight™ components.

See the Arm® CoreSight™ Architecture Specification v3.0 for information on the CoreSight ID scheme.

Table 8-2 Cortex‑A5 PIL debug memory map

APB address range Components Comments
0x00000000-0x00000FFF ROM table Start of external view of debug memory space
0x00010000-0x00010FFF Processor 0 debug components The processor internally uses paddrdbg[12] to separate debug from the PMU
0x00012000-0x00012FFF Processor 0 PMU -
0x00013000-0x00013FFF Processor 1 debug components -
0x00017000-0x00017FFF Processor 3 PMU -
0x00018000-0x00018FFF CTI0 There is one CTI for each processor
0x0001B000-0x0001BFFF CTI3 -
0x0001C000-0x0001CFFF ETM0 There is one ETM for each processor, or one shared ETM for all processors
0x0001F000-0x0001FFFF ETM3 -
0x00020000-0x00020FFF Internal view of ROM table Start of internal debug view of debug memory space
0x00030000-0x00030FFF Processor 0 debug components Location for self hosted debug access to processor debug components
0x00031000-0x00031FFF Processor 0 PMU Internal view
0x0003F000-0x0003FFFF ETM3 Internal view
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