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Alternate tracedata pins are set, with the others clear.
The pattern is effectively 64 bits wide, with bits[63:32] =
0x55555555 and bits[31:0] =
The Current Port Size Register (CSPSR) sets the width of tracedata (tracedata-width). When pattern generation starts, tracedata is aligned with the 64-bit pattern bit and tracedata-width bits of the pattern are output on tracedata[tracedata-width-1:0]. On the next rising edge of traceclk, the pattern is shifted to the right by the width of tracedata. The next tracedata-width pattern bits, starting at bit[tracedata-width], then outputs on tracedata. This sequence is repeated until all 64 bits of the pattern are consumed, at which point the pattern repeats.
Example 1 - tracedata is 8 bits wide.
In this example, the tracedata width is 8 bits. As the 8-bit tracedata width is a convenient fraction of the 64-bit repeating pattern, tracedata takes the values AA, AA, AA, AA, 55, 55... as the pattern is shifted right.
Example 2 - tracedata is 5 bits wide.
In this example, the tracedata width is 5 bits. This time, tracedata does not follow the corresponding pattern byte values. The tracedata values are 0A, 15, 0A, 15, 0A, 15, 16, 0A...
This pattern can be used to check voltage levels, cross talk, and data edge timing.