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This register captures the values of the flushin and trigin inputs in integration mode. In functional mode, this register behaves as RAZ/WI.
The ITTRFLIN register characteristics are:
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-307 ITTRFLIN register bit assignments
Read-As-Zero, Writes Ignored.
Integration status of flushin input. In integration mode, this bit latches to 1 on a rising edge of the flushin input. It is cleared when the register is read or when integration mode is disabled.
Integration status of trigin input. In integration mode, this bit latches to 1 on a rising edge of the trigin input. It is cleared when the register is read or when integration mode is disabled.