1 Features

Features and capabilities that the SoC-600 provides include:

  • Arm® Debug Interface Architecture Specification ADIv6.0-compliant debug port. This debug port supports JTAG and Serial Wire protocols for connection to an off-chip debugger. This connection is achieved using a low-pin-count connection that is suitable for bare-metal debug and silicon bring-up.
  • Arm® CoreSight™ Architecture Specification v3.0 compliance enables debug over functional interfaces, suitable for application development and in-field debug without a dedicated debug interface.
  • Infrastructure components supporting system identification and integration with other CoreSight IP.
  • Versatile Trace Memory Controller (TMC) supporting local on-chip storage, and buffering of trace data.
  • TMC router configuration supports efficient hand-off of trace data to other system masters. This feature enables trace over functional interfaces, suitable for application development and in-field debug without a dedicated debug and trace interface.
  • TMC streaming configuration supports integration to third-party High Speed Serial Trace Ports (HSSTP) for high bandwidth, low pin count trace solutions.
  • Infrastructure components supporting filtering and routing of trace data on chip.
Embedded Cross Triggering
  • Cross Trigger Interface (CTI) supports up to 32 trigger inputs and outputs with a single component instance.
  • Cross Trigger Matrix (CTM) supports up to 33 CTI or CTM connections without cascading.
  • Arm® CoreSight™ Architecture Specification v3.0-compliant Granular Power Requester (GPR) enables fine-grained debug and system power control at all levels of debug hierarchy.
  • Components are designed for low-power implementation, supporting clock and power quiescence and wakeup signaling where necessary.
  • Components support Q-Channel Low-Power Interfaces (LPI) for integration with power controllers to support system-level clock and power gating where necessary.
  • Infrastructure components support implementation across multiple clock and power domains.
  • Some components, such as the bridges and Serial Wire Debug Port (SW-DP), use two Verilog modules to span clock and power domains. This design can ease implementation in complex SoC designs that have multiple clock and power domains.
  • Infrastructure components support integration with legacy IP including Arm® CoreSight™ Architecture Specification v2.0-compliant, and JTAG components.
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