9 Current Test Patterns/Modes Register, CTPMR

This register indicates the current test pattern or mode selected. Only one of the two mode bits, bits[17:16], can be set at any one time, but a multiple number of bits for the patterns can be set using bits [3:0]. When timed mode is selected, after the allotted number of cycles is reached, the mode automatically switches to off mode. The pattern with higher bit index is output first when multiple patterns are selected. When no pattern is selected then a default pattern (00/00) is used instead. In continuous mode, the pattern generator continues to send patterns until CTPMR.PCONTEN bit is cleared by software. If multiple patterns are enabled, after sending out all enabled patterns, the pattern generator switches back to the first pattern type and continues to do so until stopped by software. When no pattern is selected then the default pattern (00/00) is used instead. Writing to this register when timed or continuous pattern mode is already enabled causes the current pattern generation to be abandoned and to be restarted with the new pattern mode and new pattern set. Writing to TPRCR or CSPSR when timed or continuous pattern mode is already enabled causes the current pattern generation to be abandoned and to be restarted. The reset value of this register is 0x00000000 which indicates off mode with no selected patterns.

The CTPMR register characteristics are:

Attributes
Offset

0x0204

Type

Read-write

Reset

0x00000000

Width

32

The following figure shows the bit assignments.

Figure 9-451 CTPMR register bit assignments
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The following table shows the bit assignments.

Table 9-466 CTPMR register bit assignments

Bits Reset value Name Function
[31:18] 0b00000000000000 RAZ/WI

Read-As-Zero, Writes Ignored.

[17] 0b0 PCONTEN

Continuous Pattern Mode. Indicates whether continuous pattern mode is enabled.

0

Mode disabled.

1

Mode enabled.

[16] 0b0 PTIMEEN

Timed Pattern Mode. Indicates whether timed pattern mode is enabled.

0

Mode disabled.

1

Mode enabled.

[15:4] 0b000000000000 RAZ/WI

Read-As-Zero, Writes Ignored.

[3] 0b0 PATF0

FF/00 Pattern. Indicates whether the FF/00 pattern is enabled as output over the Trace Port. All pins toggle simultaneously as 1-0-1-0.

0

Pattern disabled.

1

Pattern enabled.

[2] 0b0 PATA5

AA/55 Pattern. Indicates whether the AA/55 pattern is enabled as output over the Trace Port. The odd numbered pins toggle as 1-0-1-0, while the even numbered pins toggle as 0-1-0-1, simultaneously.

0

Pattern disabled.

1

Pattern enabled.

[1] 0b0 PATW0

Walking 0 Pattern. Indicates whether the walking 0s pattern is enabled as output over the Trace port. To start with, all pins are set to 1, except tracedata[0] which is driven LOW. In each subsequent cycle, the 0 bit shifts to its left by 1 position and eventually rotates around from its starting position, based on the CSPSR value, to tracedata[0], provided the pattern mode remains enabled for a sufficient number of cycles. When timed mode is selected, after the allotted number of cycles is reached (See TPRCR, 0x208), the wsmode automatically switches to off mode. The pattern with higher bit index is output first when multiple patterns are selected. When no pattern is selected then a default pattern (00/00) is used instead.

0

Pattern disabled.

1

Pattern enabled.

[0] 0b0 PATW1

Walking 1s Pattern. Indicates whether the walking 1s pattern is enabled as output over the Trace Port. It is similar to the walking 0s pattern except that tracedata[0] is set to 1 to start with and all other bits are 0. It is this set bit that rotates through all the selected pins of the tracedata port.

0

Pattern disabled.

1

Pattern enabled.

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