8 Cortex®‑M3 PIL debug memory map

The debug components in the Cortex®‑M3 PIL share memory space with the processor system. Part of the system memory is allocated to the Private Peripheral Bus (PPB).

The following tables show the locations of the Cortex‑M3 PIL CoreSight™ components.

Table 8-14 External PPB division

Address range Components
0xE0041000-0xE0041FFF ETM trace unit.
0xE0042000-0xE0042FFF CTI.
0xE00FF000-0xE00FFFFF ROM table.
0xE0040000-0xE0040FFF External PPB expansion bus. In a standard single processor Cortex‑M3 system, the Cortex‑M3 TPIU uses this space.
0xE0043000-0xE00FEFFF External PPB expansion bus.

Table 8-15 Internal PPB division

Address range Section Components
0xE0000000-0xE003FFFF Internal PPB

These components are:

  • Instrumentation Trace Macrocell (ITM).
  • Data Watchpoint and Trace (DWT).
  • Flash Patch and Breakpoint (FPB).
  • System Control Space (SCS) including for example:

    • Nested Vectored Interrupt Controller (NVIC).

    • SysTick.
    • Memory Protection Unit (MPU).
0xE0040000-0xE00FFFFF External PPB

These components are:

  • ROM table.
  • Embedded Trace Macrocel (ETM) trace unit.
  • Cross Trigger Interface (CTI).
Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.