Arm® CoreSight™ System-on-Chip SoC-600 Technical Reference Manual

Revision r3p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Typographic conventions
Timing diagrams
Signals
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1 About CoreSight SoC-600
1 Features
1 Supported standards
1 Documentation
1 Design process
1 css600 component list
1 Product revisions
2 DAP components functional description
2 Debug Port
2 Memory Access Ports
2 APB Access Port
2 AHB Access Port
2 AXI Access Port
2 AXI-AP features
2 DAP transfer abort
2 Additional AXI error responses
2 AXI transfers
2 Valid combinations of AxCACHE and AxDOMAIN
2 Error response handing
2 JTAG Access Port
2 Access Port v1 Adapter
2 DP Abort replicator
2 DP Abort asynchronous bridge
2 DP Abort synchronous bridge
2 JTAG to SWJ adapter
2 SWJ to JTAG adapter
2 SWJ interconnect
3 APB infrastructure components functional description
3 APB interconnect
3 Arbitration
3 Error response
3 APB ROM table
3 APB asynchronous bridge
3 APB synchronous bridge
3 APB PADDRDBG31 Adapter
3 APB3 to APB4 adapter
3 APB4 to APB3 adapter
4 ATB infrastructure components functional description
4 ATB upsizer
4 ATB downsizer
4 ATB funnel
4 ATB replicator
4 ATB trace buffer
4 ATB asynchronous bridge
4 ATB synchronous bridge
4 Trace Memory Controller
4 TMC register access dependencies
4 Writes to TMC registers
4 Reads from TMC registers
4 Clock and reset
4 Interfaces
4 Debug APB interface
4 ATB slave interface
4 ATB master interface
4 Memory interface
4 AXI master interface
4 AXI stream master interface
4 Clock Q-Channel Low-Power Interface
4 Event interfaces
4 Buffer interrupt interface
4 Authentication interface
4 Operation
4 Architectural state machine
4.1 DISABLED
4.2 RUNNING
4.3 STOPPING
4.4 STOPPED
4.5 DRAINING
4.6 DISABLING
4 About the Trace Port Interface Unit
4 Clocks and resets
4 Functional interfaces
4 Trace out port
4 Signals of the trace out port
4 Trace port triggers
4 Correlation with afvalid
4 Programming the TPIU for trace capture
4 Example configuration scenarios
4 Capturing trace after an event, and stopping
4 Only indicating triggers, and continuing to flush
4 Multiple trigger indications
4 Independent triggering and flushing
4 TPIU pattern generator
4 Pattern generator modes of operation
4 Supported options
4.1 Walking 1s
4.2 Walking 0s
4.3 Alternating AA/55 pattern
4.4 Alternating FF/00 pattern
4.5 Combinations of patterns
4 CoreSight™ Address Translation Unit
4 Interfaces
4 Low-Power interface
4 APB slave
4 AXI master
4 AXI slave
4 Interrupt
4 Authentication
4 Software interfaces
4 Scatter list
4 Programming the scatter list walker
4 Address validation
4 Initializing the CATU
4 Reprogramming the CATU
4 Error handling
4 Unpredictable behavior
5 Timestamp components functional description
5 Timestamp generator
5 Timestamp replicator
5 Timestamp interpolator
5 Functional interface
5 Low-Power Interface
5 Limitations
5 Narrow timestamp asynchronous bridge
5 Operation
5 Low-power features
5 Timestamp protection from slow clock
5 Narrow timestamp synchronous bridge
5 Operation
5 Low-power features
5 Narrow timestamp decoder
5 Narrow timestamp encoder
5 Narrow timestamp replicator
6 Embedded Cross Trigger components functional description
6 About cross triggering
6 Event signaling protocol
6 Cross Trigger Interface
6 asicctrl
6 Cross Trigger Matrix
6 Event Pulse to Event adapter
6 Event to Event Pulse adapter
6 Event Level asynchronous bridge
6 Event Level synchronous bridge
6 Event Pulse asynchronous bridge
6 Event Pulse synchronous bridge
6 Channel Pulse to Channel adapter
6 Channel to Channel Pulse adapter
6 Channel Pulse asynchronous bridge
6 Channel Pulse synchronous bridge
6 CTI to STM adapter
7 Authentication components functional description
7 Authentication replicator
7 Authentication asynchronous bridge
7 Authentication synchronous bridge
8 Processor Integration Layer components
8 Cortex-A5 PIL overview
8 Cortex®‑A5 PIL CoreSight component identification
8 Cortex®‑A5 PIL debug memory map
8 Cortex-A8 PIL overview
8 Cortex®‑A8 PIL CoreSight component identification
8 Cortex®‑A8 PIL debug memory map
8 Cortex-A9 PIL overview
8 Cortex®‑A9 PIL CoreSight component identification
8 Cortex®‑A9 PIL debug memory map
8 Cortex-R4 PIL overview
8 Cortex®‑R4 PIL CoreSight component identification
8 Cortex®‑R4 PIL debug memory map
8 Cortex-R5 PIL overview
8 Cortex®‑R5 PIL CoreSight component identification
8 Cortex®‑R5 PIL debug memory map
8 Cortex-M0 PIL overview
8 Cortex®‑M0 PIL CoreSight component identification
8 Cortex®‑M0 PIL debug memory map
8 Cortex-M3 PIL overview
8 Cortex®‑M3 PIL CoreSight component identification
8 Cortex®‑M3 PIL debug memory map
8 Cortex-M4 PIL overview
8 Cortex®‑M4 PIL CoreSight component identification
8 Cortex®‑M4 PIL debug memory map
9 Programmers model
9 css600 components programmers model
9 css600_dp introduction
9 Register summary
9 Register descriptions
9 AP Abort Register, ABORT
9 Debug Port Identification Register, DPIDR
9 Debug Port Identification Register 1, DPIDR1
9 Base Pointer Register 0, BASEPTR0
9 Base Pointer Register 1, BASEPTR1
9 Control/Status Register, CTRLSTAT
9 Data Link Control Register, DLCR
9 Target Identification Register, TARGETID
9 Data Link Protocol Identification Register, DLPIDR
9 Event Status Register, EVENTSTAT
9 Select Register 1, SELECT1
9 Read Resend Register, RESEND
9 Select Register, SELECT
9 Read Buffer Register, RDBUFF
9 Target Selection Register, TARGETSEL
9 css600_apbap introduction
9 Register summary
9 Register descriptions
9 Direct Access Register 0, DAR0
9 Direct Access Register 1, DAR1
9 Direct Access Register 2, DAR2
9 Direct Access Register 255, DAR255
9 Control Status Word register, CSW
9 Transfer Address Register, TAR
9 Data Read/Write register, DRW
9 Banked Data register 0, BD0
9 Banked Data register 1, BD1
9 Banked Data register 2, BD2
9 Banked Data register 3, BD3
9 Transfer Response Register, TRR
9 Configuration register, CFG
9 Debug Base Address register, BASE
9 Identification Register, IDR
9 Integration Test Status register, ITSTATUS
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Authentication Status Register, AUTHSTATUS
9 Device Architecture Register, DEVARCH
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_ahbap introduction
9 Register summary
9 Register descriptions
9 Direct Access Register 0, DAR0
9 Direct Access Register 1, DAR1
9 Direct Access Register 2, DAR2
9 Direct Access Register 255, DAR255
9 Control Status Word register, CSW
9 Transfer Address Register, TAR
9 Data Read/Write register, DRW
9 Banked Data register 0, BD0
9 Banked Data register 1, BD1
9 Banked Data register 2, BD2
9 Banked Data register 3, BD3
9 Transfer Response Register, TRR
9 Configuration register, CFG
9 Debug Base Address register, BASE
9 Identification Register, IDR
9 Integration Test Status register, ITSTATUS
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Authentication Status Register, AUTHSTATUS
9 Device Architecture Register, DEVARCH
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_axiap introduction
9 Register summary
9 Register descriptions
9 Direct Access Register 0, DAR0
9 Direct Access Register 1, DAR1
9 Direct Access Register 2, DAR2
9 Direct Access Register 255, DAR255
9 Control Status Word register, CSW
9 Transfer Address Register, TAR
9 Data Read/Write register, DRW
9 Banked Data register 0, BD0
9 Banked Data register 1, BD1
9 Banked Data register 2, BD2
9 Banked Data register 3, BD3
9 Memory Barrier Transfer register, MBT
9 Transfer Response Register, TRR
9 Configuration register, CFG
9 Debug Base Address register, BASE
9 Identification Register, IDR
9 Integration Test Status register, ITSTATUS
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Authentication Status Register, AUTHSTATUS
9 Device Architecture Register, DEVARCH
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_apv1adapter introduction
9 Register summary
9 Register descriptions
9 Integration Test Status register, ITSTATUS
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Authentication Status Register, AUTHSTATUS
9 Device Architecture Register, DEVARCH
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_jtagap introduction
9 Register summary
9 Register descriptions
9 Control/Status Word register, CSW
9 Port Select register, PSEL
9 Port Status register, PSTA
9 Byte FIFO Registers, BFIFO1
9 Byte FIFO Registers, BFIFO2
9 Byte FIFO Registers, BFIFO3
9 Byte FIFO Registers, BFIFO4
9 Identification Register, IDR
9 Integration Test Status register, ITSTATUS
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Device Architecture Register, DEVARCH
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_apbrom introduction
9 Register summary
9 Register descriptions
9 ROM Entries register 0, ROMEntry0
9 ROM Entries register 1, ROMEntry1
9 ROM Entries register 2, ROMEntry2
9 ROM Entries register 511, ROMEntry511
9 Authentication Status Register, AUTHSTATUS
9 Device Architecture Register, DEVARCH
9 Device Configuration Register, DEVID
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_apbrom_gpr introduction
9 Register summary
9 Register descriptions
9 ROM Entries register 0, ROMEntry0
9 ROM Entries register 1, ROMEntry1
9 ROM Entries register 2, ROMEntry2
9 ROM Entries register 511, ROMEntry511
9 Debug Power Control Register 0, DBGPCR0
9 Debug Power Control Register 1, DBGPCR1
9 Debug Power Control Register 2, DBGPCR2
9 Debug Power Control Register 31, DBGPCR31
9 Debug Power Status Register 0, DBGPSR0
9 Debug Power Status Register 1, DBGPSR1
9 Debug Power Status Register 2, DBGPSR2
9 Debug Power Status Register 31, DBGPSR31
9 System Power Control Register 0, SYSPCR0
9 System Power Control Register 1, SYSPCR1
9 System Power Control Register 2, SYSPCR2
9 System Power Control Register 31, SYSPCR31
9 System Power Status Register 0, SYSPSR0
9 System Power Status Register 1, SYSPSR1
9 System Power Status Register 2, SYSPSR2
9 System Power Status Register 31, SYSPSR31
9 Power Request ID Register, PRIDR0
9 Debug Reset Request Register, DBGRSTRR
9 Debug Reset Acknowledge Register, DBGRSTAR
9 System Reset Request Register, SYSRSTRR
9 System Reset Acknowledge Register, SYSRSTAR
9 Authentication Status Register, AUTHSTATUS
9 Device Architecture Register, DEVARCH
9 Device Configuration Register, DEVID
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_atbfunnel_prog introduction
9 Register summary
9 Register descriptions
9 Funnel Control register, FUNNELCONTROL
9 Priority Control register, PRIORITYCONTROL
9 Integration test data register, ITATBDATA0
9 Integration test control register 3, ITATBCTR3
9 Integration test control register 2, ITATBCTR2
9 Integration test control register 1, ITATBCTR1
9 Integration test control register 0, ITATBCTR0
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Device Affinity register 0, DEVAFF0
9 Device Affinity register 1, DEVAFF1
9 Authentication Status Register, AUTHSTATUS
9 Device Architecture Register, DEVARCH
9 Device Configuration Register 2, DEVID2
9 Device Configuration Register 1, DEVID1
9 Device Configuration Register, DEVID
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_atbreplicator_prog introduction
9 Register summary
9 Register descriptions
9 ID filtering control 0 register, IDFILT0
9 ID filtering control 1 register, IDFILT1
9 Integration Test Control register, ITATBCTRL
9 Integration Test Status register, ITATBSTAT
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Device Affinity register 0, DEVAFF0
9 Device Affinity register 1, DEVAFF1
9 Authentication Status Register, AUTHSTATUS
9 Device Architecture Register, DEVARCH
9 Device Configuration Register 2, DEVID2
9 Device Configuration Register 1, DEVID1
9 Device Configuration Register, DEVID
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_tmc_etb introduction
9 Register summary
9 Register descriptions
9 RAM Size register, RSZ
9 Status register, STS
9 RAM Read Data register, RRD
9 RAM Read Pointer register, RRP
9 RAM Write Pointer register, RWP
9 Trigger Counter register, TRG
9 Control Register, CTL
9 RAM Write Data register, RWD
9 Mode register, MODE
9 Latched Buffer Fill Level, LBUFLEVEL
9 Current Buffer Fill Level, CBUFLEVEL
9 Buffer Level Water Mark, BUFWM
9 Formatter and Flush Status Register, FFSR
9 Formatter and Flush Control Register, FFCR
9 Periodic Synchronization Counter Register, PSCR
9 Integration Test Event and Interrupt Control Register, ITEVTINTR
9 Integration Test Trigger In and Flush In register, ITTRFLIN
9 Integration Test ATB Data 0 Register, ITATBDATA0
9 Integration Test ATB Control 2 Register, ITATBCTR2
9 Integration Test ATB Control 1 Register, ITATBCTR1
9 Integration Test ATB Control 0 Register, ITATBCTR0
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Authentication Status Register, AUTHSTATUS
9 Device Configuration Register 1, DEVID1
9 Device Configuration Register, DEVID
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_tmc_etf introduction
9 Register summary
9 Register descriptions
9 RAM Size register, RSZ
9 Status register, STS
9 RAM Read Data register, RRD
9 RAM Read Pointer register, RRP
9 RAM Write Pointer register, RWP
9 Trigger Counter register, TRG
9 Control Register, CTL
9 RAM Write Data register, RWD
9 Mode register, MODE
9 Latched Buffer Fill Level, LBUFLEVEL
9 Current Buffer Fill Level, CBUFLEVEL
9 Buffer Level Water Mark, BUFWM
9 Formatter and Flush Status Register, FFSR
9 Formatter and Flush Control Register, FFCR
9 Periodic Synchronization Counter Register, PSCR
9 Integration Test ATB Master Data 0 register, ITATBMDATA0
9 Integration Test ATB Master Control 2 register, ITATBMCTR2
9 Integration Test ATB Master Control 1 register, ITATBMCTR1
9 Integration Test Event and Interrupt Control Register, ITEVTINTR
9 Integration Test Trigger In and Flush In register, ITTRFLIN
9 Integration Test ATB Data 0 Register, ITATBDATA0
9 Integration Test ATB Control 2 Register, ITATBCTR2
9 Integration Test ATB Control 1 Register, ITATBCTR1
9 Integration Test ATB Control 0 Register, ITATBCTR0
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Authentication Status Register, AUTHSTATUS
9 Device Configuration Register 1, DEVID1
9 Device Configuration Register, DEVID
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_tmc_etr introduction
9 Register summary
9 Register descriptions
9 RAM Size register, RSZ
9 Status register, STS
9 RAM Read Data register, RRD
9 RAM Read Pointer register, RRP
9 RAM Write Pointer register, RWP
9 Trigger Counter register, TRG
9 Control Register, CTL
9 RAM Write Data register, RWD
9 Mode register, MODE
9 Latched Buffer Fill Level, LBUFLEVEL
9 Current Buffer Fill Level, CBUFLEVEL
9 Buffer Level Water Mark, BUFWM
9 RAM Read Pointer High register, RRPHI
9 RAM Write Pointer High register, RWPHI
9 AXI Control Register, AXICTL
9 Data Buffer Address Low register, DBALO
9 Data Buffer Address HIGH register, DBAHI
9 RAM Update Read Pointer register, RURP
9 Formatter and Flush Status Register, FFSR
9 Formatter and Flush Control Register, FFCR
9 Periodic Synchronization Counter Register, PSCR
9 Integration Test ATB Master Control 0 register, ITATBMCTR0
9 Integration Test Event and Interrupt Control Register, ITEVTINTR
9 Integration Test Trigger In and Flush In register, ITTRFLIN
9 Integration Test ATB Data 0 Register, ITATBDATA0
9 Integration Test ATB Control 2 Register, ITATBCTR2
9 Integration Test ATB Control 1 Register, ITATBCTR1
9 Integration Test ATB Control 0 Register, ITATBCTR0
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Authentication Status Register, AUTHSTATUS
9 Device Configuration Register 1, DEVID1
9 Device Configuration Register, DEVID
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_tmc_ets introduction
9 Register summary
9 Register descriptions
9 RAM Size register, RSZ
9 Status register, STS
9 RAM Read Data register, RRD
9 Trigger Counter register, TRG
9 Control Register, CTL
9 RAM Write Data register, RWD
9 Mode register, MODE
9 Formatter and Flush Status Register, FFSR
9 Formatter and Flush Control Register, FFCR
9 Periodic Synchronization Counter Register, PSCR
9 Integration Test Event and Interrupt Control Register, ITEVTINTR
9 Integration Test Trigger In and Flush In register, ITTRFLIN
9 Integration Test ATB Data 0 Register, ITATBDATA0
9 Integration Test ATB Control 2 Register, ITATBCTR2
9 Integration Test ATB Control 1 Register, ITATBCTR1
9 Integration Test ATB Control 0 Register, ITATBCTR0
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Authentication Status Register, AUTHSTATUS
9 Device Configuration Register 1, DEVID1
9 Device Configuration Register, DEVID
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_tpiu introduction
9 Register summary
9 Register descriptions
9 Supported Port Size Register, SSPSR
9 Current Port Size Register, CSPSR
9 Supported Trigger Modes Register, STMR
9 Trigger Counter Value Register, TCVR
9 Trigger Counter Multiplier Register, TCMR
9 Supported Test Patterns/Modes Register, STPMR
9 Current Test Patterns/Modes Register, CTPMR
9 Test Pattern Repeat Counter Register, TPRCR
9 Formatter and Flush Status Register, FFSR
9 Formatter and Flush Control Register, FFCR
9 Formatter Synchronization Count Register, FSCR
9 External Control Port In Register, EXTCTLIN
9 External Control Port Out Register, EXTCTLOUT
9 Integration Test Trigger In and Flush In Register, ITTRFLIN
9 Integration Test ATB Data Register 0, ITATBDATA0
9 Integration Test ATB Control Register 2, ITATBCTR2
9 Integration Test ATB Control Register 1, ITATBCTR1
9 Integration Test ATB Control Register 0, ITATBCTR0
9 Integration Test Output Control Register, ITOUTCTR
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Authentication Status Register, AUTHSTATUS
9 Device Architecture Register, DEVARCH
9 Device Configuration Register, DEVID
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_catu introduction
9 Register summary
9 Register descriptions
9 CATU control register, CONTROL
9 Mode register, MODE
9 AXI control register, AXICTRL
9 Interrupt enable register, IRQEN
9 Scatter List Address Low register, SLADDRLO
9 Scatter List Address High register, SLADDRHI
9 Input Address Low register, INADDRLO
9 Input Address High register, INADDRHI
9 Status register, STATUS
9 Integration Test Interrupt register, ITIRQ
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Authentication Status Register, AUTHSTATUS
9 Device Architecture Register, DEVARCH
9 Device Configuration Register, DEVID
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 css600_tsgen introduction
9 Register summary
9 Register summary
9 Register descriptions
9 Counter Control Register, CNTCR
9 Current value of Counter[31:0], CNTCVLREAD
9 Counter Status Register, CNTSR
9 Current value of Counter[63:32], CNTCVUREAD
9 Current value of Counter[31:0], CNTCVL
9 Current value of Counter[63:32], CNTCVU
9 Base Frequency ID register, CNTFID0
9 Integration Test Status Register, ITSTAT
9 Integration Mode Control Register, ITCTRL
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
9 Component Identification Register 3, CIDR3
9 css600_cti introduction
9 Register summary
9 Register descriptions
9 CTI Control register, CTICONTROL
9 CTI Interrupt Acknowledge register, CTIINTACK
9 CTI Application Channel Set register, CTIAPPSET
9 CTI Application Channel Clear register, CTIAPPCLEAR
9 CTI Application Channel Pulse register, CTIAPPPULSE
9 CTI Trigger 0 to Channel Enable register, CTIINEN0
9 CTI Trigger 1 to Channel Enable register, CTIINEN1
9 CTI Trigger 2 to Channel Enable register, CTIINEN2
9 CTI Trigger 31 to Channel Enable register, CTIINEN31
9 CTI Channel to Trigger 0 Enable register, CTIOUTEN0
9 CTI Channel to Trigger 1 Enable register, CTIOUTEN1
9 CTI Channel to Trigger 2 Enable register, CTIOUTEN2
9 CTI Channel to Trigger 31 Enable register, CTIOUTEN31
9 CTI Trigger Input Status register, CTITRIGINSTATUS
9 CTI Trigger Output Status register, CTITRIGOUTSTATUS
9 CTI Channel Input Status register, CTICHINSTATUS
9 CTI Channel Output Status register, CTICHOUTSTATUS
9 Enable CTI Channel Gate register, CTIGATE
9 External Multiplexer Control register, ASICCTRL
9 Integration Test Channel Output register, ITCHOUT
9 Integration Test Trigger Output register, ITTRIGOUT
9 Integration Test Channel Input register, ITCHIN
9 Integration Test Trigger Input register, ITTRIGIN
9 Integration Mode Control Register, ITCTRL
9 Claim Tag Set Register, CLAIMSET
9 Claim Tag Clear Register, CLAIMCLR
9 Device Affinity register 0, DEVAFF0
9 Device Affinity register 1, DEVAFF1
9 Authentication Status Register, AUTHSTATUS
9 Device Architecture Register, DEVARCH
9 Device Configuration Register, DEVID
9 Device Type Identifier Register, DEVTYPE
9 Peripheral Identification Register 4, PIDR4
9 Peripheral Identification Register 5, PIDR5
9 Peripheral Identification Register 6, PIDR6
9 Peripheral Identification Register 7, PIDR7
9 Peripheral Identification Register 0, PIDR0
9 Peripheral Identification Register 1, PIDR1
9 Peripheral Identification Register 2, PIDR2
9 Peripheral Identification Register 3, PIDR3
9 Component Identification Register 0, CIDR0
9 Component Identification Register 1, CIDR1
9 Component Identification Register 2, CIDR2
9 Component Identification Register 3, CIDR3
A Revisions
A Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 01 March 2017 Non-Confidential First release for r0p0
0000-01 11 May 2017 Non-Confidential Second release for r0p0
0100-00 01 August 2017 Non-Confidential First release for r1p0
0200-00 08 December 2017 Non-Confidential First release for r2p0
0300-00 18 May 2018 Non-Confidential First release for r3p0

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