9 Register summary

The following table shows the registers in offset order from the base memory address.

Note:

A reset value containing one or more '-' means that this register contains UNKNOWN or IMPLEMENTATION-DEFINED values. See the relevant register description for more information.

Locations that are not listed in the table are Reserved.

The 8KB memory map contains two views of the registers, one starting at 0x00000000, and the other at 0x00001000. In the case of RW registers, the two views provide independent physical registers. Writing to a RW register in one view does not affect the contents of the same register in the other view. For all read-only registers, the two views provide read access to the same physical register. In this case, reading from either view results in the same data being read.

Table 9-17 css600_apbap - APB4_Slave_0 register summary

Offset

Name

Type

Reset

Width

Description

0x0000

DAR0

RW

0x--------

32

Direct Access Register 0, DAR0

0x0004

DAR1

RW

0x--------

32

Direct Access Register 1, DAR1

0x0008

DAR2

RW

0x--------

32

Direct Access Register 2, DAR2

0x03FC

DAR255

RW

0x--------

32

Direct Access Register 255, DAR255

0x0D00

CSW

RW

0x30-000-2

32

Control Status Word register, CSW

0x0D04

TAR

RW

0x--------

32

Transfer Address Register, TAR

0x0D0C

DRW

RW

0x--------

32

Data Read/Write register, DRW

0x0D10

BD0

RW

0x--------

32

Banked Data register 0, BD0

0x0D14

BD1

RW

0x--------

32

Banked Data register 1, BD1

0x0D18

BD2

RW

0x--------

32

Banked Data register 2, BD2

0x0D1C

BD3

RW

0x--------

32

Banked Data register 3, BD3

0x0D24

TRR

RW

0x00000000

32

Transfer Response Register, TRR

0x0DF4

CFG

RO

0x000101A0

32

Configuration register, CFG

0x0DF8

BASE

RO

0x-----00-

32

Debug Base Address register, BASE

0x0DFC

IDR

RO

0x14770006

32

Identification Register, IDR

0x0EFC

ITSTATUS

RW

0x00000000

32

Integration Test Status register, ITSTATUS

0x0F00

ITCTRL

RW

0x00000000

32

Integration Mode Control Register, ITCTRL

0x0FA0

CLAIMSET

RW

0x00000003

32

Claim Tag Set Register, CLAIMSET

0x0FA4

CLAIMCLR

RW

0x00000000

32

Claim Tag Clear Register, CLAIMCLR

0x0FB8

AUTHSTATUS

RO

0x000000--

32

Authentication Status Register, AUTHSTATUS

0x0FBC

DEVARCH

RO

0x47700A17

32

Device Architecture Register, DEVARCH

0x0FCC

DEVTYPE

RO

0x00000000

32

Device Type Identifier Register, DEVTYPE

0x0FD0

PIDR4

RO

0x00000004

32

Peripheral Identification Register 4, PIDR4

0x0FD4

PIDR5

RO

0x00000000

32

Peripheral Identification Register 5, PIDR5

0x0FD8

PIDR6

RO

0x00000000

32

Peripheral Identification Register 6, PIDR6

0x0FDC

PIDR7

RO

0x00000000

32

Peripheral Identification Register 7, PIDR7

0x0FE0

PIDR0

RO

0x000000E2

32

Peripheral Identification Register 0, PIDR0

0x0FE4

PIDR1

RO

0x000000B9

32

Peripheral Identification Register 1, PIDR1

0x0FE8

PIDR2

RO

0x0000001B

32

Peripheral Identification Register 2, PIDR2

0x0FEC

PIDR3

RO

0x00000000

32

Peripheral Identification Register 3, PIDR3

0x0FF0

CIDR0

RO

0x0000000D

32

Component Identification Register 0, CIDR0

0x0FF4

CIDR1

RO

0x00000090

32

Component Identification Register 1, CIDR1

0x0FF8

CIDR2

RO

0x00000005

32

Component Identification Register 2, CIDR2

0x0FFC

CIDR3

RO

0x000000B1

32

Component Identification Register 3, CIDR3

0x1000

DAR0

RW

0x--------

32

Direct Access Register 0, DAR0

0x1004

DAR1

RW

0x--------

32

Direct Access Register 1, DAR1

0x1008

DAR2

RW

0x--------

32

Direct Access Register 2, DAR2

0x13FC

DAR255

RW

0x--------

32

Direct Access Register 255, DAR255

0x1D00

CSW

RW

0x30-000-2

32

Control Status Word register, CSW

0x1D04

TAR

RW

0x--------

32

Transfer Address Register, TAR

0x1D0C

DRW

RW

0x--------

32

Data Read/Write register, DRW

0x1D10

BD0

RW

0x--------

32

Banked Data register 0, BD0

0x1D14

BD1

RW

0x--------

32

Banked Data register 1, BD1

0x1D18

BD2

RW

0x--------

32

Banked Data register 2, BD2

0x1D1C

BD3

RW

0x--------

32

Banked Data register 3, BD3

0x1D24

TRR

RW

0x00000000

32

Transfer Response Register, TRR

0x1DF4

CFG

RO

0x000101A0

32

Configuration register, CFG

0x1DF8

BASE

RO

0x-----00-

32

Debug Base Address register, BASE

0x1DFC

IDR

RO

0x14770006

32

Identification Register, IDR

0x1EFC

ITSTATUS

RW

0x00000000

32

Integration Test Status register, ITSTATUS

0x1F00

ITCTRL

RW

0x00000000

32

Integration Mode Control Register, ITCTRL

0x1FA0

CLAIMSET

RW

0x00000003

32

Claim Tag Set Register, CLAIMSET

0x1FA4

CLAIMCLR

RW

0x00000000

32

Claim Tag Clear Register, CLAIMCLR

0x1FB8

AUTHSTATUS

RO

0x000000--

32

Authentication Status Register, AUTHSTATUS

0x1FBC

DEVARCH

RO

0x47700A17

32

Device Architecture Register, DEVARCH

0x1FCC

DEVTYPE

RO

0x00000000

32

Device Type Identifier Register, DEVTYPE

0x1FD0

PIDR4

RO

0x00000004

32

Peripheral Identification Register 4, PIDR4

0x1FD4

PIDR5

RO

0x00000000

32

Peripheral Identification Register 5, PIDR5

0x1FD8

PIDR6

RO

0x00000000

32

Peripheral Identification Register 6, PIDR6

0x1FDC

PIDR7

RO

0x00000000

32

Peripheral Identification Register 7, PIDR7

0x1FE0

PIDR0

RO

0x000000E2

32

Peripheral Identification Register 0, PIDR0

0x1FE4

PIDR1

RO

0x000000B9

32

Peripheral Identification Register 1, PIDR1

0x1FE8

PIDR2

RO

0x0000001B

32

Peripheral Identification Register 2, PIDR2

0x1FEC

PIDR3

RO

0x00000000

32

Peripheral Identification Register 3, PIDR3

0x1FF0

CIDR0

RO

0x0000000D

32

Component Identification Register 0, CIDR0

0x1FF4

CIDR1

RO

0x00000090

32

Component Identification Register 1, CIDR1

0x1FF8

CIDR2

RO

0x00000005

32

Component Identification Register 2, CIDR2

0x1FFC

CIDR3

RO

0x000000B1

32

Component Identification Register 3, CIDR3

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