9 Device Configuration Register, DEVID

This register is IMPLEMENTATION DEFINED for each Part Number and Designer. The register indicates the capabilities of the component.

The DEVID register characteristics are:

Attributes
Offset

0x0FC8

Type

Read-only

Reset

0x00000-2-

Width

32

The following figure shows the bit assignments.

Figure 9-498 DEVID register bit assignments
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The following table shows the bit assignments.

Table 9-514 DEVID register bit assignments

Bits Reset value Name Function
[31:13] 0x0 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[12:8] IMPLEMENTATION_DEFINED AXIDW

This field indicates the width of the AXI data buses, in multiples of the byte-width. The width of the AXI data buses are set by the parameter AXI_DATA_WIDTH, the default value is 64-bit wide AXI data buses. For example, 0x04 = 32-bit AXI data buses, 0x08 = 64-bit AXI data buses.

[7] 0b0 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[6:0] IMPLEMENTATION_DEFINED AXIAW

This field indicates the width of the AXI address buses, in bits. The width of the AXI address buses are set by the parameter AXI_ADDR_WIDTH, the default value is 40-bit wide AXI address buses.

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