9 Port Select register, PSEL

Port Select register enables JTAG ports, provided the slave interface is connected to the JTAG AP and port_enabled signal from the slave interface to the JTAG AP is asserted HIGH. The port select register must be written only when the following conditions are met: the JTAG engine is idle AND the write FIFO is empty. If this register is written to in any other state, the corresponding JTAG ports are abruptly enabled, or disabled, in the middle of a transfer, which might cause errors, stalls, or deadlocks in the JTAG slave.

The PSEL register characteristics are:









The following figure shows the bit assignments.

Figure 9-139 PSEL register bit assignments
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The following table shows the bit assignments.

Table 9-145 PSEL register bit assignments

Bits Reset value Name Function
[31:8] 0x0 RAZ/WI

Read-As-Zero, Writes Ignored.

[7:0] 0b00000000 PSELn

Port Select. Each register field is named as PSELn, where n = 0-7. The numerical index represents the bit position of that field in this register.

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