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This register controls the values of event and interrupt outputs in integration mode. In functional mode, this register behaves as RAZ/WI. In integration mode, the value that is written to any bit of this register is driven on the output pin that is controlled by that bit and the reads return
The ITEVTINTR register characteristics are:
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-350 ITEVTINTR register bit assignments
Read-As-Zero, Writes Ignored.
Controls the value of flushcomp output in integration mode.
Controls the value of full output in integration mode.
Controls the value of acqcomp output in integration mode.