9 Port Status register, PSTA

The Port Status register captures the state of a connected and selected port on every clock cycle. If a connected and selected port is disabled or powered down, that is signal port_enabled goes low, even transiently, the corresponding bit in the PSTA register is set in the next cycle. It remains 1 until it is cleared by writing 1 to it. It gets cleared automatically on abort. Deselecting a port in PSEL does not alter the state of PSTA. If the PSTA bit is set for a port, that port is disabled and its TCK, TMS, and TDI outputs are driven LOW until its PSTA bit is cleared. Software must not clear any PSTA bit unless the JTAG-AP is idle, that is CSW.SERACTV=0b0 and CSW.WFIFOCNT=0x0.

The PSTA register characteristics are:

Attributes
Offset

0x0D08

Type

Read-write

Reset

0x00000000

Width

32

The following figure shows the bit assignments.

Figure 9-140 PSTA register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 9-146 PSTA register bit assignments

Bits Reset value Name Function
[31:8] 0x0 RAZ/WI

Read-As-Zero, Writes Ignored.

[7:0] 0b00000000 PSTAn

Port Status. Each register field is named as PSTAn, where n = 0-7. The numerical index represents the bit position of that field in this register.

Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.