9 CATU control register, CONTROL

This register is the global enable register for the CATU. Setting the ENABLE bit enables the CATU. When the CATU is disabled, any received AXI transactions result in an error response. STATUS.READY must be HIGH before the CATU is enabled. See the ARM AMBA AXI and ACE Protocol Specification for information on the bit encodings.

The CONTROL register characteristics are:

Attributes
Offset

0x0000

Type

Read-write

Reset

0x00000000

Width

32

The following figure shows the bit assignments.

Figure 9-483 CONTROL register bit assignments
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The following table shows the bit assignments.

Table 9-499 CONTROL register bit assignments

Bits Reset value Name Function
[31:1] 0x0 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[0] 0b0 ENABLE

Enables the CATU.

0

CATU is disabled.

1

CATU is enabled.

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