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This register is the global enable register for the CATU. Setting the ENABLE bit enables the CATU. When the CATU is disabled, any received AXI transactions result in an error response. STATUS.READY must be HIGH before the CATU is enabled. See the ARM AMBA AXI and ACE Protocol Specification for information on the bit encodings.
The CONTROL register characteristics are:
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-499 CONTROL register bit assignments
Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.
Enables the CATU.