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Home > Programmers model > css600_tmc_etr introduction > Register descriptions > Integration Test ATB Master Control 0 register, ITATBMCTR0 |
This register enables control of the ATB master outputs atbytes_m, atwakeup_m, afready_m, and atvalid_m in integration mode. In functional mode, this register behaves as RAZ/WI. In integration mode, the value that is written to any bit of this register is driven on the output pin that is controlled by that bit, and the reads return 0x0
.
The ITATBMCTR0 register characteristics are:
Offset |
|
Type | Write-only |
Reset |
|
Width | 32 |
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-397 ITATBMCTR0 register bit assignments
Bits | Reset value | Name | Function |
---|---|---|---|
[31:12] | 0x0 |
RAZ/WI | Read-As-Zero, Writes Ignored. |
[11:8] | 0b0000 |
ATBYTESM | Controls the value of atbytes_m output in integration mode. This width of this field is given by N=8+log2(ATB DATA WIDTH/8). |
[7:3] | 0b00000 |
RAZ/WI | Read-As-Zero, Writes Ignored. |
[2] | 0b0 |
ATWAKEUPM | Controls the value of atwakeup_m output in integration mode. |
[1] | 0b0 |
AFREADYM | Controls the value of afready_m output in integration mode. |
[0] | 0b0 |
ATVALIDM | Controls the value of atvalid_m output in integration mode. |