9 Integration Test Event and Interrupt Control Register, ITEVTINTR

This register controls the values of event and interrupt outputs in integration mode. In functional mode, this register behaves as RAZ/WI. In integration mode, the value that is written to any bit of this register is driven on the output pin that is controlled by that bit and the reads return 0x0.

The ITEVTINTR register characteristics are:

Attributes
Offset

0x0EE0

Type

Write-only

Reset

0x00000000

Width

32

The following figure shows the bit assignments.

Figure 9-295 ITEVTINTR register bit assignments
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The following table shows the bit assignments.

Table 9-306 ITEVTINTR register bit assignments

Bits Reset value Name Function
[31:3] 0x0 RAZ/WI

Read-As-Zero, Writes Ignored.

[2] 0b0 FLUSHCOMP

Controls the value of flushcomp output in integration mode.

[1] 0b0 FULL

Controls the value of full output in integration mode.

[0] 0b0 ACQCOMP

Controls the value of acqcomp output in integration mode.

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