9 Formatter Synchronization Count Register, FSCR

The FSCR register indicates the maximum number of formatter frames that are sent to Trace Port after which a synchronization packet must be inserted. The register value indicates the programmed counter value and not the current state of the counter. The TPIU uses a frame sync counter that contains the number of formatter frames since the last frame synchronization packet. The counter is a 12-bit counter with a maximum count value of 4096. This equates to synchronization every 65536 bytes (4096 packets x 16 bytes per packet). On reset, the FSCR is set up for a synchronization packet every 1024 bytes, that is every 64 formatter frames. If the formatter is configured in continuous mode, full and half-word sync frames are inserted during normal operation. In this case, the counter value is the maximum number of complete frames between full synchronization packets.

The FSCR register characteristics are:

Attributes
Offset

0x0308

Type

Read-write

Reset

0x00000040

Width

32

The following figure shows the bit assignments.

Figure 9-455 FSCR register bit assignments
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The following table shows the bit assignments.

Table 9-470 FSCR register bit assignments

Bits Reset value Name Function
[31:12] 0x0 RAZ/WI

Read-As-Zero, Writes Ignored.

[11:0] 0b000001000000 CycCount

12-bit counter value to indicate the number of complete frames between full synchronization packets. It is also used to send periodic synchronization requests to the ATB master using syncreq_s output. If this field is programmed as 0x0, the synchronization counter is disabled. The reset value is 0x040, that is, 64 frames = 1024 bytes.

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