9 Control Status Word register, CSW

The CSW register configures and controls accesses through the APB master interface to the connected memory system.

The CSW register characteristics are:

Attributes
Offset

0x0D00

Type

Read-write

Reset

0x30-000-2

Width

32

The following figure shows the bit assignments.

Figure 9-20 CSW register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 9-22 CSW register bit assignments

Bits Reset value Name Function
[31] 0b0 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[30:28] 0b011 Prot

Drives APB master interface pprot_m[2:0] which specifies the APB4 protection encoding. The reset value is 0x3 (Data, Non-secure, Privileged). Together with authentication interface signals, CSW.Prot[1] determines whether a Secure access is allowed on the master interface as follows, access = dbgen && spiden || dbgen && CSW.Prot[1].

[27:24] 0b0000 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[23] UNKNOWN SDeviceEn

Indicates the status of the spiden and spniden ports. It is set when either spiden or spniden is HIGH, and remains clear otherwise. If this bit is clear, Secure APB master transfers are not permitted. Non-secure memory accesses and internal register accesses that do not initiate memory accesses are permitted regardless of the status of this bit.

[22:18] 0b00000 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[17] 0b0 ERRSTOP

Stop on error. Reset to 0.

0

Memory access errors do not prevent future memory accesses.

1

Memory access errors prevent future memory accesses.

[16] 0b0 ERRNPASS

Errors that are not passed upstream. Reset to 0.

0

Memory access errors that are passed upstream.

1

Memory access errors that are not passed upstream.

[15:12] 0b0000 Type

This field is reserved. Reads return 0x0 and writes are ignored.

[11:8] 0b0000 Mode

Specifies the mode of operation. Reset to 0x0. All other values are reserved.

0x0

Normal download or upload mode.

[7] 0b0 TrInProg

Transfer in progress. This field indicates whether a transfer is in progress on the APB master interface.

[6] UNKNOWN DeviceEn

Indicates the status of dbgen and niden ports. The bit is set when either dbgen or niden is HIGH, and is clear otherwise. If this bit is clear, no APB master transfers are carried out, that is, both Secure and Non-secure accesses are blocked.

[5:4] 0b00 AddrInc

Auto address increment mode on RW data access. Only increments if the current transaction completes without an error response and the transaction is not aborted. Reset to 0b0.

0x0

Auto increment OFF.

0x1

Increment, single. Single transfer from corresponding byte lane.

0x2

Reserved.

0x3

Reserved.

[3] 0b0 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

[2:0] 0b010 Size

Size of the data access to perform. The APB-AP supports only word accesses and this field is fixed at 0x2. The reset value is 0x2.

Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.