9 Input Address Low register, INADDRLO

This register, together with the INADDRHI register, enables the CATU to validate the input address on the AXI slave interface. It gives the lower 32 bits of the lower value of the valid input address range. Software must program the INADDRLO register with an initial value before setting CONTROL.ENABLE bit to 1. It is writable only when CONTROL.ENABLE is clear and STATUS.READY is set.

The INADDRLO register characteristics are:

Attributes
Offset

0x0028

Type

Read-write

Reset

0x---00000

Width

32

The following figure shows the bit assignments.

Figure 9-489 INADDRLO register bit assignments
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The following table shows the bit assignments.

Table 9-505 INADDRLO register bit assignments

Bits Reset value Name Function
[31:20] UNKNOWN INADDRLO

Holds bits [31:12] of the lower 32 bits of the lower value of the valid AXI address range.

[19:0] 0x0 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.

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