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This register allows observability and controllability of the SYNCREQ signals into, and out of, the funnel. Only one slave interface must be selected for integration test. The syncreq receiver on the master interface has a latching function to capture a pulse arriving on that input. The arrival of a pulse sets the latch so that the value can be read. Reading the register clears the latch. Reading a 1 indicates that a syncreq_m pulse arrived since the last read. Reading a 0 indicates that no syncreq_m pulse has arrived. Writing a 1 to the register causes a syncreq_s pulse to be generated to the upstream component.
The ITATBCTR3 register characteristics are:
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-235 ITATBCTR3 register bit assignments
Software should write the field as all 0s.
Reads and controls the SYNCREQ signals into, and out of, the funnel. Reading clears the latch.