9 Direct Access Register 1, DAR1

The Direct Access Registers provide a mechanism for directly mapping locations in the target memory system that is connected to the APB master interface.

The DAR1 register characteristics are:

Attributes
Offset

0x0004

Type

Read-write

Reset

0x--------

Width

32

The following figure shows the bit assignments.

Figure 9-85 DAR1 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 9-89 DAR1 register bit assignments

Bits Reset value Name Function
[31:0] UNKNOWN Data

Maps to memory address ((TAR & 0xFFFFFC00) + 0x4.) In read mode, the register contains the data value that was read from memory, and in write mode the register contains the data value to write to memory.

Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.