9 Status register, STS

Indicates the status of the Trace Memory Controller. After a reset, software must ignore all the fields of this register except STS.TMCReady. The other fields have meaning only when the TMC has left the Disabled state. Writes to all RO fields of this register are ignored.

The STS register characteristics are:

Attributes
Offset

0x000C

Type

Read-write

Reset

0x000000--

Width

32

The following figure shows the bit assignments.

Figure 9-321 STS register bit assignments
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The following table shows the bit assignments.

Table 9-333 STS register bit assignments

Bits Reset value Name Function
[31:5] UNKNOWN RAZ/WI

Read-As-Zero, Writes Ignored.

[4] UNKNOWN Empty

Trace buffer empty. If set, this bit indicates that the trace memory does not contain any valid trace data. However, this does not mean that the pipeline stages within the TMC are empty. To determine whether the internal pipeline stages are empty, the software must read the STS.TMCReady bit.

[3] UNKNOWN FtEmpty

Formatter pipeline empty. This bit is deprecated and is present in this register to support backwards compatibility with earlier versions of the ETB. It is set when trace capture has stopped, and all internal pipelines and buffers have drained. Unlike STS.TMCReady, it is not affected by buffer drains and AXI accesses. It is cleared to 0 when leaving the Disabled state and retains its value when entering the Disabled state.

[2] 0b1 TMCReady

TMC ready. This flag is set when trace capture has stopped and all internal pipelines and buffers have drained, the TMC is not draining as a result of FFCR.DrainBuffer bit being set (ETF only), and the AXI interface is not busy and the response for final AXI write has been received (ETR only) are all true. This bit is cleared to 0 when leaving the Disabled state and retains its value when entering the Disabled state.

[1] UNKNOWN Triggered

TMC triggered. This bit is set when trace capture is in progress and the TMC has detected a trigger event. This bit is cleared to 0 when leaving the Disabled state and retains its value when entering the Disabled state. A trigger event is when the TMC has written a set number of data words, as programmed in the TRG register, into the trace memory after a rising edge of trigin input, or a trigger packet (atid_s = 0x7D) is received in the input trace.

[0] UNKNOWN Full

Trace memory full. This bit helps in determining the amount of valid data present in the trace memory. It is not affected by the reprogramming of pointer registers in Disabled state. It is cleared when the TMC leaves Disabled state.

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