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Home > Programmers model > css600_dp introduction > Register descriptions > Control/Status Register, CTRLSTAT |
The Control/Status register provides control of the DP and status information about the DP.
The CTRLSTAT register characteristics are:
Offset |
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Type | Read-write |
Reset |
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Width | 32 |
The following figure shows the bit assignments.
The following table shows the bit assignments.
Table 9-7 CTRLSTAT register bit assignments
Bits | Reset value | Name | Function | ||||
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[31] | Unknown | CSYSPWRUPACK | System powerup acknowledge. Status of CSYSPWRUPACK interface signal. |
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[30] | 0b0 |
CSYSPWRUPREQ | System powerup request. This bit controls the CSYSPWRUPREQ signal on the interface. |
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[29] | Unknown | CDBGPWRUPACK | Debug powerup acknowledge. Status of CDBGPWRUPACK interface signal. |
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[28] | 0b0 |
CDBGPWRUPREQ | Debug powerup request. This bit controls the CDBGPRWUPREQ signal on the interface. |
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[27] | Unknown | CDBGRSTACK | Debug reset acknowledge. Indicates the status of the CDBGRSTACK signal on the interface. |
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[26] | 0b0 |
CDBGRSTREQ | Debug reset request. This bit controls the CDBGRSTREQ signal on interface. |
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[24] | 0b0 |
ERRMODE | Error Mode.
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[7] | 0b0 |
WDATAERR | This bit is DATA LINK DEFINED, such that on a JTAG-DP this bit is reserved, RES0, and on an SW-DP this bit is RO. This bit is set to 1 if a Write Data Error occurs. This happens if there is a parity or framing error on the data phase of a write, or a write that has been accepted by the DP is then discarded without being submitted to the AP. On an SW-DP, this bit is cleared to 0 by writing 1 to the ABORT.WDERRCLR bit. |
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[6] | 0b0 |
READOK | This flag always indicates the response to the last AP read access. This bit is DATA LINK DEFINED. On JTAG-DP, the bit is reserved, RES0, and on SW-DP, access is RO. If the response to the previous AP read or RDBUFF read was OK, then the bit is set to 1. If the response was not OK, then it is cleared to 0. |
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[5] | 0b0 |
STICKYERR |
If an error is returned by an AP transaction, and CTRLSTAT.ERRMODE is b0, then this bit is set to 1. The behavior on writing is DATA LINK DEFINED: On a JTAG-DP, access is R/W1C. On a SW-DP, access is RO/WI. Clearing this bit to 0 is also DATA LINK DEFINED: On a JTAG-DP, the bit is cleared by writing 1 to this bit, or by writing 1 to the ABORT.STKERRCLR field. On SW-DP, the bit is cleared by writing 1 to the ABORT.STKERRCLR field. |
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[1] | 0b0 |
STICKYORUN |
If overrun detection is enabled, this bit is set to 1 when an overrun occurs. The behavior on writing is DATA LINK DEFINED: on a JTAG-DP, access is R/W1C. On a SW-DP, access is RO/WI. Clearing this bit to 0 is also DATA LINK DEFINED: On a JTAG-DP, the bit is cleared by writing 1 to this bit, or by writing 1 to the ABORT.ORUNERRCLR field. On SW-DP, the bit is cleared by writing 1 to the ABORT.ORUNERRCLR field. |
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[0] | 0b0 |
ORUNDETECT | This bit is set to 1 to enable overrun detection. |