Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Arm® CoreSight™ System-on-Chip SoC-600 Technical Reference ManualRevision r3p0
Home > Programmers model > css600_apbrom_gpr introduction > Register descriptions > Peripheral Identification Register 4, PIDR4

9 Peripheral Identification Register 4, PIDR4

The PIDR4 register is part of the set of peripheral identification registers.

The PIDR4 register characteristics are:

Attributes
Offset

0x0FD0
Type

Read-only
Reset

0x00000004
Width

32

The following figure shows the bit assignments.

Figure 9-211 PIDR4 register bit assignments
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


The following table shows the bit assignments.

Table 9-219 PIDR4 register bit assignments

Bits Reset value Name Function
[31:8] 0x0 RES0

Reserved bit or field with Should-Be-Zero-or-Preserved (SBZP) behavior.
[7:4] 0b0000 SIZE

Indicates the memory size that is used by this component. Returns 0 indicating that the component uses an UNKNOWN number of 4KB blocks. Using the SIZE field to indicate the size of the component is deprecated.
[3:0] 0b0100 DES_2

JEP106 continuation code. Together, with PIDR2.DES_1 and PIDR1.DES_0, they indicate the designer of the component and not the implementer, except where the two are the same.
Non-ConfidentialPDF file icon PDF version100806_0300_00_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved. 
Home > Programmers model > css600_apbrom_gpr introduction > Register descriptions > Peripheral Identification Register 4, PIDR4